ELECTRONIC DEVICE WAFER LEVEL SCALE PACKAGES AND FABRICATION METHODS THEREOF

• US 20110237018A1
• Filed: 06/03/2011
• Published: 09/29/2011
• Est. Priority Date: 08/24/2007
• Status: Active Grant

• Current Assignee: Chien-Hung Liu, Sih-Dian Lee
• Original Assignee: Chien-Hung Liu, Sih-Dian Lee
• Inventors: LIU, Chien-Hung, Lee, Sih-Dian
• Granted Patent: US 8,309,398 B2
• Time in Patent Office: Days
• US Class Current: 438/73
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 27/14618 Containers
• CPC Class Codes: H01L 27/14687 Wafer level processing
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01023 Vanadium [V]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/12043 Photo diode
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 31/0203 Containers; Encapsulations , e.g. encapsulation of photodiodesfor photovoltaic devices H01L31/048; for organic photosensitive devices H10K30/80

Abstract

Electronic device wafer level scale packages and fabrication methods thereof A semiconductor wafer with a plurality of electronic devices formed thereon is provided. The semiconductor wafer is bonded with a supporting substrate. The back of the semiconductor substrate is thinned. A first trench is formed by etching the semiconductor exposing an inter-layered dielectric layer. An insulating layer is conformably deposited on the back of the semiconductor substrate. The insulating layer on the bottom of the first trench is removed to create a second trench. The insulating layer and the ILD layer are sequentially removed exposing part of a pair of contact pads. A conductive layer is conformably formed on the back of the semiconductor. After the conductive layer is patterned, the conductive layer and the contact pads construct an S-shaped connection. Next, an exterior connection and terminal contact pads are subsequently formed.

Claims

1. A fabrication method for an electronic device chip scale package, comprising:

providing a semiconductor wafer with a plurality of electronic devices thereon;

bonding the semiconductor wafer with a supporting substrate and thinning the back of the semiconductor wafer;

etching the back of the semiconductor wafer to create a first opening;

conformably depositing an insulating layer on the back of the semiconductor wafer;

etching the insulating layer at the bottom of the first opening and creating a second opening exposing part of contact pads, the exposed part of the contact pads comprising a vertical portion and a horizontal portion, wherein the second opening extends over upper surfaces of the contact pads, and lower surfaces of the contact pads are between the upper surfaces and the semiconductor wafer;

after the second opening is created, conformably depositing a conductive layer on the back of the semiconductor wafer and patterning the conductive layer, thereby creating an S-shaped connection constructed by the conductive layer and the contact pads;

forming exterior connections and terminal contact pads connecting the S-shaped connection; and

forming a dam structure between the semiconductor wafer and the supporting substrate, wherein the second opening extends into the dam structure, and a bottom surface of the second opening is between upper surfaces of the dam structure and the upper surfaces of the contact pads.

2. The fabrication method as claimed in claim 1, wherein the plurality of electronic devices comprise an integrated circuit device, an optoelectronic device, an electromechanical device, or a surface acoustic wave (SAW) device.

3. The fabrication method as claimed in claim 2, wherein the optoelectronic device comprises a CMOS image sensing device.

4. The fabrication method as claimed in claim 1, wherein the supporting substrate is transparent comprising lens quality glass or quartz.

5. The fabrication method as claimed in claim 1, wherein deposition techniques of the insulating layer comprises spray coating, sputtering, printing, application and spin coating.

6. The fabrication method as claimed in claim 1, wherein the insulating layer comprises epoxy, polyimide, resin, silicon oxide, metal oxide, or silicon nitride.

7. The fabrication method as claimed in claim 1, after deposition of the insulating layer, further comprising:

forming a patterned mask layer on the insulating layer exposing the insulating layer at the bottom of the first opening; and

etching the exposed insulating layer at the bottom of the first opening using the patterned mask layer.

8. The fabrication method as claimed in claim 1, further comprises cutting the semiconductor wafer and the supporting substrate to divide each electronic device chip scale package.

9. The fabrication method as claimed in claim 1, wherein the conductive layer extends into the second opening.

10. The fabrication method as claimed in claim 9, wherein the conductive layer conformally extends on a bottom and a sidewall of the second opening.