Formation of Active Area Using Semiconductor Growth Process without STI Integration

• US 20110237035A1
• Filed: 06/09/2011
• Published: 09/29/2011
• Est. Priority Date: 07/15/2004
• Status: Active Grant

• Current Assignee: Danny Pak-Chum Shum, Jiang Yan
• Original Assignee: Danny Pak-Chum Shum, Jiang Yan
• Inventors: Yan, Jiang, Shum, Danny Pak-Chum
• Granted Patent: US 8,173,502 B2
• Time in Patent Office: Days
• US Class Current: 438/197
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02639 Preparation of substrate for selective deposition

Abstract

A semiconductor device can be formed without use of an STI process. An insulating layer is formed over a semiconductor body. Portions of the insulating layer are removed to expose the semiconductor body, e.g., to expose bare silicon. A semiconductor material, e.g., silicon, is grown over the exposed semiconductor body. A device, such as a transistor, can then be formed in the grown semiconductor material.

Claims

1. A method of making a semiconductor device, the method comprising:

providing a semiconductor substrate having a top surface;

forming a plurality of isolation regions above the substrate;

forming a plurality of active areas of semiconductor material above the semiconductor substrate and adjacent the isolation regions so that each active area is isolated from another active area by an isolation region, each active area having an interface at the substrate where semiconductor material of the active area touches semiconductor material of the substrate, wherein said active areas have an interface at the top surface of the substrate where said semiconductor material of the active areas touches semiconductor material of the substrate; and

forming a plurality of transistors, each transistor at least two doped regions disposed within the semiconductor material of an active area and an electrode disposed over the semiconductor material of that active area.

2. The method of claim 1 wherein the active areas have a thickness and wherein the isolation structures have a thickness and wherein the thickness of the active areas is about equal to the thickness of the isolation structures.

3. The method of claim 2 wherein the thickness of the isolation structures and the thickness of the active areas are between 100 nm and 500 nm.

4. The method of claim 1 wherein each transistor comprises an MOS transistor that includes a source and a drain region disposed within the semiconductor material of the active area and a gate electrode disposed over the semiconductor material of the active area.

5. The method of claim 4 wherein some of the active areas are doped with n-type impurities.

6. The method of claim 4 wherein some of the active areas are doped with p-type impurities.

7. The method of claim 4 wherein some of the active areas are doped with n-type impurities and others of the active areas are doped with p-type impurities and wherein forming a plurality of transistors comprises forming CMOS transistors.

8. The method of claim 1 wherein forming a plurality of transistors comprises forming bipolar transistors.

9. The method of claim 1 wherein the isolation structures comprise oxide regions.

10. The method of claim 1 wherein the isolation structures comprise nitride regions.

11. The method of claim 1 wherein the isolation structures comprise high-k dielectric regions.

12. The method of claim 1 wherein the semiconductor material of the active area is the same material as the semiconductor material of the semiconductor substrate.

13. A method of making a semiconductor device, the method comprising:

providing a semiconductor substrate having a top surface;

forming a plurality of isolation regions above the substrate;

forming a plurality of active areas of semiconductor material above the semiconductor substrate and adjacent the isolation regions so that each active area is isolated from another active area by an isolation region, each active area having an interface at the substrate where semiconductor material of the active area touches semiconductor material of the substrate, said active areas having a top surface at the same level as said top surface of said isolation structures, wherein an interface between the surface of the substrate and the active area is undetectable in cross-sectional view; and

forming a plurality of transistors within said active areas, each transistor comprising at least two doped regions disposed within the semiconductor material of an active area and an electrode disposed over the semiconductor material of that active area.

14. A method of making a semiconductor device, the method comprising:

providing a semiconductor substrate having a top surface;

forming a first and a second isolation structure, the first and the second isolation structure forming a gap between the first and the second isolation structures;

growing semiconductor material from said top surface of said semiconductor substrate in the gap between the first and the second isolation structures; and

forming a transistor having a first doped region and a second doped region disposed in the grown semiconductor material.

15. The method of claim 14, wherein the grown semiconductor material comprises an active area having a top surface at the same level as said top surface of the first and the second isolation structures.

16. The method of claim 14, wherein the transistor comprises a bipolar transistor.

17. The method of claim 14 wherein some of the active areas are doped with n-type impurities.

18. The method of claim 14 wherein some of the active areas are doped with p-type impurities.

19. The method of claim 14, wherein the transistor comprises a field effect transistor.

20. The method of claim 14 wherein some of the active areas are doped with n-type impurities and others of the active areas are doped with p-type impurities and wherein forming a plurality of transistors comprises forming CMOS transistors.