MAIN SPACER TRIM-BACK METHOD FOR REPLACEMENT GATE PROCESS

• US 20110237040A1
• Filed: 03/24/2010
• Published: 09/29/2011
• Est. Priority Date: 03/24/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: WU, Sin-Hua, CHUANG, Harry-Hak-Lay, YOUNG, Bao-Ru, NG, Jin-Aun, HSU, Yu-Ying, LEE, Chi-Ju
• Granted Patent: US 8,039,388 B1
• Time in Patent Office: Days
• US Class Current: 438/303
• CPC Class Codes: H01L 21/823425 manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects

Abstract

The embodiments of methods described in this disclosure for trimming back nitride spacers for replacement gates allows the hard mask layers (or hard mask) to protect the polysilicon above the high-K dielectric during trim back process. The process sequence also allows determining the trim-back amount based on the process uniformity (or control) of nitride deposition and nitride etchback (or trimming) processes. Nitride spacer trim-back process integration is critical to avoid creating undesirable consequences, such as silicided polyisicon on top of high-K dielectric described above. The integrated process also allows widening the space between the gate structures to allow formation of silicide with good quality and allow contact plugs to have sufficient contact with the silicide regions. The silicide with good quality and good contact between the contact plugs and the silicide regions increase the yield of contact and allows the contact resistance to be in acceptable and workable ranges.

Claims

1. A method of trimming back main spacers of replacement gate structures on a substrate, comprising:

forming main spacers for replacement gate structures on the substrate, wherein the replacement gate structures have a dielectric layer, a dummy layer over the dielectric layer, and a hard mask over the dummy layer;

performing source and drain implants, wherein source and drain patterns are formed to allow source and drain implants to be performed on desired regions of the substrate and the source and drain patterns are removed from the substrate after the source and drain implants are performed;

trimming back the main spacers to increase a space between two adjacent replacement gate structures on the substrate to allow proper formation of metal silicide by subsequent processing;

after said trimming back, performing source and drain anneal; and

forming the metal silicide on the substrate.

3. The method of claim 1, further comprising:

implanting polysilicon on the substrate before the forming of the metal silicide, wherein the implanted polysilicon improves the quality of the metal silicide formed, and wherein the trimming back of the main spacers reduces a shadowing effect of polysilicon implant.

4. The method of claim 1, wherein the forming of the metal silicide on the substrate comprises:

depositing a silicide metal layer on the substrate, wherein the trimming back of the main spacers improves the step coverage of the deposition of the silicide metal layer; and

annealing the substrate to form the metal silicide.

5. The method of claim 1, wherein the main spacers are trimmed back to a minimal thickness of about 50 Å

across the substrate.

6. The method of claim 1, wherein the trimming back of the main spacers is accomplished by using phosphorous acid (H₃PO₄) at about 120°

C. for from about 1 minute to about 3 minutes.

7. The method of claim 1, wherein the performing of the source and drain anneal comprises:

depositing a protective oxide on the substrate;

annealing the substrate to drive dopants in the source and drain regions into the substrate, wherein the protective oxide layer is deposited on the substrate before the substrate is annealed to prevent boron out-gassing; and

patterning the protective oxide layer after the annealing of the substrate to allow the metal silicide to be formed on a part of the substrate.

9. The method of claim 1, wherein the trimming back of the main spacers increases landing areas for contact plugs to be formed on the metal silicide.

10. The method of claim 1, wherein a silicide metal used for forming the metal silicide is selected from the group consisting of titanium, cobalt, nickel, platinum, and tungsten.

11. The method of claim 1, further comprising:

after forming the metal silicide on the substrate, further trimming back the main spacers to increase the space between two adjacent replacement gate structures on the substrate.

21. The method of claim 1, wherein

a thin oxide layer is formed on the substrate as a result of the removal of the source and drain patterns, and

the method further comprises removing the thin oxide layer before the main spacers are trimmed back.

2. A method of trimming back main nitride spacers of replacement gate structures on a substrate, comprising:

forming main nitride spacers for replacement gate structures on the substrate, wherein the replacement gate structures have a high dielectric constant (high-K) dielectric layer, a dummy polysilicon layer over the high-K dielectric layer, and a hard mask with an oxide layer over a nitride layer;

performing source and drain implants, wherein source and drain patterns are formed to allow source and drain implants to be performed on desired regions of the substrate and the source and drain patterns are removed from the substrate after the source and drain implants are performed;

trimming back the main nitride spacers to increase a space between two adjacent replacement gate structures on the substrate to allow proper formation of metal silicide by subsequent processing and to increase contact yield;

performing source and drain anneal; and

forming the metal silicide on the substrate;

wherein

a thin oxide layer formed on the substrate as a result of the removal of the source and drain patterns, and

the method further comprises removing the thin oxide layer before the main nitride spacers are trimmed back.

8. The method of claim 2, the thin oxide layer formed on the substrate as a result of removing of the source and drain patterns is removed by using a 100:

1 diluted HF solution for from about 10 seconds to about 1 minute.

12. A method of trimming back main nitride spacers of replacement gate structures on a substrate, comprising:

forming main nitride spacers for replacement gate structures on the substrate, wherein the replacement gate structures have a high dielectric constant (high-K) dielectric layer and a dummy polysilicon layer over the high-K dielectric layer, and a hard mask with an oxide layer over a nitride layer;

performing source and drain implants, wherein source and drain patterns are formed to allow source and drain implants to be performed on desired regions of the substrate and the source and drain patterns are removed from the substrate after the source and drain implants are performed;

performing first trim-back of the main nitride spacers to increase a space between two adjacent replacement gate structures on the substrate to allow proper formation of metal silicide by subsequent processing and to increase contact yield;

performing source and drain anneal;

implanting polysilicon on the substrate before the forming of the metal silicide, wherein the implanted polysilicon improves the quality of the metal silicide formed, and wherein the first trim-back of the main nitride spacers reduces shadowing effect of polysilicon implant;

forming the metal silicide on the substrate; and

performing second trim-back of the main nitride spacers to increase the space between two adjacent replacement gate structures on the substrate to further increase the contact yield.

13. The method of claim 12, wherein

a thin oxide layer is formed on the substrate as a result of the removal of the source and drain patterns, and

the method further comprises removing the thin oxide layer before the first trim-back.

14. The method of claim 12, wherein the forming of the metal silicide on the substrate further comprises:

depositing a silicide metal layer on the substrate, wherein the first trim-back of the main nitride spacers improves the step coverage of the deposition of the silicide metal layer; and

annealing the substrate to form the metal silicide.

15. The method of claim 12, wherein the main nitride spacers are trimmed back to a minimal thickness of about 50 Å

across the substrate.

16. The method of claim 12, wherein each of the first and second trim-back of the main nitride spacers is accomplished by using phosphorous acid (H₃PO₄) at about 120°

C. for between about 60 seconds to about 180 seconds.

17. The method of claim 13, wherein the performing of the source and drain anneal comprises:

depositing a protective oxide on the substrate;

annealing the substrate to drive dopants in the source and drain regions into the substrate, wherein the protective oxide layer is deposited on the substrate before the substrate is annealed to prevent boron out-gassing; and

patterning the protective oxide layer after the annealing of the substrate to allow the metal silicide to be formed on a part of the substrate.

18. The method of claim 13, wherein the thin oxide layer formed on the substrate as a result of removing of the source and drain patterns is removed by using a 100:

1 diluted HF solution for from about 10 seconds to about 1 minute.

19. The method of claim 12, wherein a silicide metal used for forming the metal silicide is selected from the group consisting of titanium, cobalt, nickel, platinum, and tungsten.

20. A method of trimming back main nitride spacers of replacement gate structures on a substrate, comprising:

forming main nitride spacers for replacement gate structures on the substrate, wherein the replacement gate structures have a high dielectric constant (high-K) dielectric layer, a dummy polysilicon layer over the high-K dielectric layer, and a hard mask with an oxide layer over a nitride layer;

performing source and drain implants, wherein source and drain patterns are formed to allow source and drain implants to be performed on desired regions of the substrate and the source and drain patterns are removed from the substrate after the source and drain implants are performed;

performing first trim-back of the main nitride spacers to increase a space between two adjacent replacement gate structures on the substrate to allow proper formation of metal silicide by subsequent processing;

performing source and drain anneal;

forming the metal silicide on the substrate; and

performing second trim-back of the main nitride spacers to increase the space between two adjacent replacement gate structures on the substrate.