Semiconductor Device And Method Of Fabricating The Same

• US 20110237062A1
• Filed: 03/23/2011
• Published: 09/29/2011
• Est. Priority Date: 03/24/2010
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Hong, Sughun, Hyun, Sangjin, Park, Hongbae, Na, Hoonjoo, Shin, Yugyun, Lee, Hye-Lan, Hong, Hyung-seok
• Granted Patent: US 8,309,411 B2
• Time in Patent Office: Days
• US Class Current: 438/592
• CPC Class Codes: H01L 21/28 Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268 etching for patterning the electrodes H01L21/311, H01L21/3213; multistep manufacturing processes for data storage electrodes H01L29/4011
• CPC Class Codes: H01L 21/8234 MIS technology , i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 29/49 Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET H01L29/435 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Abstract

A method of fabricating a semiconductor device includes forming an interlayer dielectric on a substrate, the interlayer dielectric including first and second openings respectively disposed in first and second regions formed separately in the substrate; fondling a first conductive layer filling the first and second openings; etching the first conductive layer such that a bottom surface of the first opening is exposed and a portion of the first conductive layer in the second opening remains; and forming a second conductive layer filling the first opening and a portion of the second opening.

Claims

1. A method of fabricating semiconductor device, the method comprising:

forming an interlayer dielectric on a substrate, the interlayer dielectric including first and second openings respectively disposed in first and second regions formed separately in the substrate;

forming a first conductive layer filling the first and second openings;

etching the first conductive layer such that a bottom surface of the first opening is exposed and a portion of the first conductive layer in the second opening remains; and

forming a second conductive layer filling the first opening and a portion of the second opening.

2. The method of claim 1, wherein the etching the first conductive layer comprises:

forming a mask pattern covering the first conductive layer on the second region;

performing a first etching process on the first conductive layer on the first region using the mask pattern;

removing the mask pattern; and

performing a second etching process to remove a portion of the first conductive layer remaining in the first opening after the performing the first etching process and to remove a portion of the first conductive layer in the second opening.

3. The method of claim 1, further comprising:

etching the second conductive layer to remove a portion of the second conductive layer in the first opening and expose the remaining portion of the first conductive layer in the second opening.

4. The method of claim 3, further comprising:

forming a third conductive layer on the second conductive layer remaining in the first opening and on the first conductive layer remaining in the second opening, the third conductive layer filling upper regions of the first and second openings.

5. The method of claim 4, wherein the third conductive layer has a lower resistivity than the first and second conductive layers.

6. The method of claim 1, wherein:

the first conductive layer is conformally formed in the second opening, the first conductive layer having a thickness less than one-half of a width of the second opening, and

the second conductive layer is conformally formed in the first opening, the second conductive layer having a thickness less than one-half of a width of the first opening.

7. The method of claim 6, wherein, after the forming the second conductive layer,

the second conductive layer remaining in the first opening includes a bottom portion on a bottom surface of the first opening and a sidewall portion on a sidewall of the first opening, the sidewall portion having a top surface lower than a top surface of the interlayer dielectric, and

the first conductive layer remaining in the second opening includes a bottom portion on a bottom surface of the second opening and a sidewall portion on a sidewall of the second opening, the sidewall portion having a top surface lower than the top surface of the interlayer dielectric.

8. The method of claim 1, wherein the forming the interlayer dielectric comprises:

forming first and second gate dielectric patterns and first and second dummy gate pattern sequentially stacked on the respective first and second regions of the substrate, the first and second gate dielectric patterns including first and second insulation patterns and first and second metal compound patterns on the first and second insulation patterns, respectively; and

forming an interlayer dielectric material on the substrate and sidewalls of the first and second dummy gate patterns; and

removing the first and second dummy gate patterns to form the first and second openings.

9. The method of claim 8, wherein the removing the first and second dummy gate patterns includes etching the first and second dummy gate patterns using the respective first and second metal compound patterns to expose the first and second gate dielectric patterns disposed on the respective first and second regions of the substrate.

10. The method of claim 1, wherein a work function of the first conductive layer and a work function of the second conductive layer are different from each other.

11. A method of fabricating semiconductor device, the method comprising:

forming an interlayer dielectric on a substrate, the interlayer dielectric including an opening;

conformally forming a first conductive layer on a bottom surface and side wall of the opening;

etching the first conductive layer to remove a portion of the first conductive layer from an upper region of the opening such that the first conductive layer remains on a bottom portion of a bottom surface of the opening and on a sidewall portion on a sidewall of the opening, and a top surface of the sidewall portion is lower than a top surface of the interlayer dielectric; and

forming a second conductive layer filling the upper region of the opening.

12. The method of claim 11, wherein the forming the interlayer dielectric comprises:

forming a gate dielectric pattern on the substrate, the gate dielectric pattern including an insulation pattern and a metal compound pattern on the insulation pattern;

forming a dummy gate pattern on the gate dielectric pattern;

forming an interlayer dielectric material on the substrate and sidewalls of the dummy gate pattern; and

removing the dummy gate pattern.

13. The method of claim 12, wherein the removing the dummy gate pattern includes etching the dummy gate pattern using the metal compound pattern to expose the gate dielectric pattern.

14. The method of claim 11, wherein a thickness of the first conductive layer is less than one-half of a width of the opening.

15. The method of claim 11, wherein the second conductive layer has a lower resistivity than the first conductive layer.

16. The method of claim 11, wherein etching the first conductive layer includes performing an anisotropic etching process.

17-19. -19. (canceled)