DATA PROCESSING DEVICE

• US 20110238958A1
• Filed: 05/23/2011
• Published: 09/29/2011
• Est. Priority Date: 09/06/2002
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Kondo, Hiroyuki, OHTANI, Sugako
• Granted Patent: US 8,627,046 B2
• Time in Patent Office: Days
• US Class Current: 712/221
• CPC Class Codes: G06F 9/3001 Arithmetic instructions
• CPC Class Codes: G06F 9/3016 Decoding the operand specifier, e.g. specifier format
• CPC Class Codes: G06F 9/30167 of immediate specifier, e.g. constants
• CPC Class Codes: G06F 9/325 for loops, e.g. loop detection or loop counter

Abstract

A data processing device has an instruction decoder, a control logic unit, and ALU. The instruction decoder decodes instruction codes of an arithmetic instruction. The control logic unit detects the effective data width of operation data to be processed according to the decode result from the instruction decoder and determines the number of cycles for the instruction execution corresponding to the effective, data width. The ALU executes the instruction with the number of cycles of the instruction execution determined by the control logic unit.

Claims

1. A method of execution of a divide instruction for a data processor, comprising the steps of:

determining a data size of a dividend instructed in the divide instruction during an execution of the divide instruction, and

executing a divide calculation based on the divide instruction,

wherein a calculation cycle count of the divide calculation is determined depending on the data size of the dividend.

2. The method according to claim 1,

wherein the divide instruction contains information indicating whether the dividend is the signed form number or the unsigned form number, and

wherein the data size of the dividend is determined based on the information in the divide instruction.