MANAGEMENT OF A NON-VOLATILE MEMORY BASED ON TEST QUALITY

• US 20110239064A1
• Filed: 03/24/2010
• Published: 09/29/2011
• Est. Priority Date: 03/24/2010
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Byom, Matthew, Post, Daniel J., Wakrat, Nir J., Herman, Kenneth
• Granted Patent: US 8,650,446 B2
• Time in Patent Office: Days
• US Class Current: 714/723
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 2029/4402 Internal storage of test result, quality data, chip identification, repair information
• CPC Class Codes: G11C 29/10 Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns
• CPC Class Codes: G11C 29/42 using error correcting codes [ECC] or parity check
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair
• CPC Class Codes: G11C 29/56008 Error analysis, representation of errors

Abstract

Systems and methods are disclosed for managing a non-volatile memory (“NVM”), such as a flash memory. The NVM may be managed based on results of a test performed on the NVM. The test may indicate, for example, physical memory locations that may be susceptible to errors, such as certain pages in the blocks of the NVM. Tests on multiple NVMs of the same type may be compiled to create a profile of error tendencies for that type of NVM. In some embodiments, data may be stored in the NVM based on individual test results for the NVM or based on a profile of the NVM type. For example, memory locations susceptible to error may be retired or data stored in those memory locations may be protected by a stronger error correcting code.

Claims

1. A method of configuring a memory system comprising a non-volatile memory, the method comprising:

performing a test on a plurality of physical memory locations in a non-volatile memory, wherein results of the test indicate which of the physical memory locations failed the test;

identifying, from the results, a pattern of physical memory locations tending to fail the test; and

managing the physical memory locations of the non-volatile memory based on the pattern.

2. The method of claim 1, wherein the test is performed during a manufacturing process of the memory system.

3. The method of claim 1, wherein the managing comprises configuring the memory system to access the non-volatile memory based on the pattern.

4. The memory system of claim 3, wherein the configuring is performed during a manufacturing process of the memory system.

5. The memory system of claim 1, wherein the identifying comprises determining, from the test results, pages of the non-volatile memory with corresponding page numbers that have a percentage of failure greater than a predetermined threshold.

6. The method of claim 1, wherein the managing comprises configuring the memory system to store data in the non-volatile memory based on the pattern.

7. The method of claim 6, wherein the configuring comprises at least one of:

retiring at least a portion of the physical memory locations based on the pattern, applying error correction to data being stored in the non-volatile memory based on the pattern, determining a number of bits per cell to use for particular physical memory locations based on the pattern, and storing particular types of data at particular physical memory locations in the non-volatile memory based on the pattern.

8. The method of claim 1, wherein the non-volatile memory comprises flash memory.

9. A method of configuring a memory system comprising a non-volatile memory, the method comprising:

testing a plurality of non-volatile memories of a particular type;

identifying memory locations in the non-volatile memories that are susceptible to error based on the testing;

creating a profile of the particular type of non-volatile memories using the identifying; and

managing a particular non-volatile memory of the particular type based on the profile.

10. The method of claim 9, wherein each of the non-volatile memories comprise a plurality of blocks each having a plurality of pages, and wherein the identifying comprises determining a proportion of corresponding pages in each block that failed their respective tests.

11. The method of claim 9, wherein the managing comprises configuring the memory system to retire at least a portion of the memory locations that are identified as being susceptible to error.

12. The method of claim 9, wherein the managing comprises:

configuring the memory system to apply a first storage technique to at least a portion of the memory locations that are identified as being susceptible to error;

configuring the memory system to apply a second storage technique to a remaining portion of the memory locations that are not identified as being susceptible to error, wherein the first storage technique is more reliable than the second storage technique.

13. The method of claim 12, wherein the first storage technique comprises applying a first error correcting code to data stored in the at least at portion of the memory locations, and wherein the second storage technique comprises applying a second error correcting code to data stored in the remaining portion of the memory locations, wherein the first error correcting code has a higher strength than the second error correcting code.

14. The method of claim 12, wherein the first storage technique uses fewer bits per cell than the second storage technique.

15. The method of claim 9, wherein the managing comprises:

determining how critical data is that is being stored in the particular non-volatile memory;

configuring the memory system to store less critical data in the memory locations that are determined to be susceptible to error.

16. The method of claim 9, further comprising:

performing an additional test on an additional non-volatile memory of the particular type; and

updating the profile using results of the additional test.

17. The method of claim 9, wherein the particular non-volatile memory is included in the plurality of non-volatile memories, and wherein the managing is performed based on the profile and the testing of the particular non-volatile memory.

18. The method of claim 9, wherein the particular non-volatile memory is not included in the plurality of non-volatile memories.

19. A memory system comprising:

a non-volatile memory comprising a plurality of blocks, wherein each of the blocks comprises a sequence of pages; and

a processor for controlling access to the pages of the non-volatile memory, wherein the processor is configured to;

manage a first set of corresponding pages in each of the blocks using a first approach, wherein the first set of corresponding pages comprise memory locations that were determined to be susceptible to error based on tests performed during a manufacturing process of the memory system; and

manage a second set of corresponding pages in each of the blocks using a second approach, wherein the second set of corresponding pages comprise memory locations that were determined not to be susceptible to error based on the tests performed during the manufacturing process of the memory system.

20. The memory system of claim 19, further comprising an integrated circuit package, wherein the non-volatile memory and the processor are included in the integrated circuit package.

21. The memory system of claim 19, further comprising an integrated circuit package, wherein the non-volatile memory is included in the integrated circuit package, and wherein the processor is implemented in a system-on-a-chip external to the integrated circuit package.

22. The memory system of claim 19, wherein the non-volatile memory comprises a NAND flash memory.

23. The memory system of claim 19, wherein the first approach comprises at least one of:

avoiding use of the first set of corresponding pages, applying error correction to data being stored in the first set that has a higher strength than the error correction used to store data in the second set, using a number of bits per cell for the first set that is less than the number used for the second set, and storing a particular type of data in the first set.