RUN-TIME TESTING OF MEMORY LOCATIONS IN A NON-VOLATILE MEMORY

• US 20110239065A1
• Filed: 03/24/2010
• Published: 09/29/2011
• Est. Priority Date: 03/24/2010
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Byom, Matthew, Khmelnitsky, Vadim, Post, Daniel J., Herman, Kenneth
• Granted Patent: US 8,645,776 B2
• Time in Patent Office: Days
• US Class Current: 714/723
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 29/42 using error correcting codes [ECC] or parity check
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: G11C 29/82 for EEPROMs

Abstract

Systems and methods are disclosed for performing run-time tests on a non-volatile memory (“NVM”), such as flash memory. The run-time tests may be tests that are performed on the NVM while the NVM can be operated by an end user (as opposed to during a manufacturing phase). In some embodiments, a controller for the NVM may detect an error event that may be indicative of a systemic failure of a die of the NVM. The controller may then select one or more blocks in the die to test, which may be dies that are currently not being used to store user data. The controller may post process the results of the test to determine whether there is a systemic failure, such as a column failure, and may treat the systemic failure if there is one.

Claims

1. A method of managing a non-volatile memory, wherein the non-volatile memory comprises at least one die having a plurality of blocks, the method comprising:

detecting an error event indicative of a systematic failure of a die of the non-volatile memory;

responsive to the detecting, selecting at least one unused block in the die;

performing a run-time test on the selected at least one unused block; and

managing the die of the non-volatile memory based on results of the run-time test.

2. The method of claim 1, further comprising:

maintaining error characteristics of the non-volatile memory,

wherein the detecting comprises identifying a criterion in the error characteristics.

3. The method of claim 2, wherein maintaining the error characteristics comprises at least one:

recording addresses of where error events are occurring in the die, keeping track of the bit error rate of the die, keeping track of the bit error rate of at least one of the blocks in the die, keeping track of the number of program or erase failures in a predetermined number of attempts, and keeping track of the number of uncorrectable error events in different blocks of the die.

4. The method of claim 1, wherein the detecting comprises detecting a pattern of errors in at least one block in the die.

5. The method of claim 1, further comprising:

performing garbage collection on another block of the die to free the block for the run-time test,

wherein performing the run-time test comprises testing the another block.

6. The method of claim 1, wherein the performing comprises performing a plurality of iterations, each of the iterations comprising:

programming the at least one unused block with a predetermined pattern;

reading the at least one unused block to verify the accuracy of the programming; and

erasing the at least one unused block.

7. The method of claim 1, further comprising:

determining, based on the run-time test, whether the error event is likely caused by a block-specific error or a die-wide error,

wherein the managing is performed based on the determining.

8. A memory system, comprising:

a non-volatile memory comprising a plurality of dies, wherein each of the dies comprises a plurality of blocks;

a controller configured to;

select one of the dies to perform a test, wherein the selected die comprises a first plurality of unused blocks and a second plurality of blocks programmed with user data;

choose at least one of the unused blocks in the selected die; and

perform the test on the chosen blocks.

9. The memory system of claim 8, wherein the controller is packaged with non-volatile memory.

10. The memory system of claim 8, wherein the controller comprises a host processor packaged externally from the non-volatile memory.

11. The memory system of claim 8, wherein the non-volatile memory comprises NAND flash memory.

12. The memory system of claim 8, wherein the controller is further configured to manage the selected die based on results of the test.

13. The memory system of claim 11, wherein the controller is further configured to identify a failure of a column along a bit line of the selected die, and wherein the controller is configured to treat the failure of the selected die by remapping the column to another column in the non-volatile memory.

14. The memory system of claim 8, wherein the controller is further configured to notify a user of die issues based on results of the test.

15. The memory system of claim 8, wherein the controller is further configured to identify, based on results of the test, at least one of a row failure, peripheral circuitry failure, and error clusters in the die.

16. A method of identifying a cause of run-time errors in a first block of a non-volatile memory, the method comprising:

performing garbage collection on the first block to free the first block for a run-time test;

selecting a second block for the run-time test, wherein the second block is on the same die as the first block;

performing run-time tests on the first and second blocks; and

comparing results of testing the first block to results of testing the second block to determine whether the errors of the first block are die-wide or block-specific.

17. The method of claim 16, further comprising:

selecting a third block for the run-time test, wherein the third block is unused and on the same die as the first and second blocks;

performing a run-time test on the third block; and

comparing results of testing the first block to results of testing the third block.

18. The method of claim 16, wherein the selecting comprises choosing the second block from erased blocks in the same die.

19. The method of claim 16, wherein the non-volatile memory comprises flash memory, and wherein the selecting comprises requesting, from a flash translation layer, a free block from the same die as the first block.

20. The method of claim 16, wherein the selecting comprises choosing the second block based on its number of erases.

21. The method of claim 16, wherein the selecting comprises requesting a physical address of an unused block from a translation layer.

22. The method of claim 16, further comprising making a die-wide change to managing the non-volatile memory in response to determining that the errors are die-wide.