ERROR DETECTION/CORRECTION CIRCUIT, MEMORY CONTROLLER AND SEMICONDUCTOR MEMORY APPARATUS

• US 20110239080A1
• Filed: 03/03/2011
• Published: 09/29/2011
• Est. Priority Date: 03/26/2010
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: ISHIKAWA, Yukio, UCHIKAWA, Hironori, SAKAUE, Kenji, ICHIKAWA, Kazuhiro, ISHIKAWA, Tatsuyuki
• Granted Patent: US 8,453,034 B2
• Time in Patent Office: Days
• US Class Current: 714/752
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: H03M 13/1117 using approximations for check node processing, e.g. an outgoing message is depending on the signs and the minimum over the magnitudes of all incoming messages according to the min-sum rule
• CPC Class Codes: H03M 13/1137 Partly parallel processing, i.e. sub-blocks or sub-groups of nodes being processed in parallel
• CPC Class Codes: H03M 13/116 Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
• CPC Class Codes: H03M 13/1188 wherein in the part with the double-diagonal at least one column has an odd column weight equal or greater than three

Abstract

An LDPC error detection/correction circuit according to an embodiment includes a selector that divides data into p groups based on a check matrix H including blocks made up of unit matrixes having a size p and shift blocks, a selector that divides a group into Y subgroups, a bit node storage section that stores LMEM variables to calculate a probability β in association with each first address, a check node storage section that stores TMEM variables to calculate an external value α in association with each second address, a rotator that performs rotation processing on the TMEM with a rotation value based on a shift value, and an operation circuit made up of (p/Y) operation units that perform parallel processing in subgroup units.

Claims

1. An error detection/correction circuit comprising:

a first selector configured to divide received data into p groups to output the groups based on a check matrix comprising a block made up of a unit matrix of a size p (p is an integer equal to or greater than

     8) and a plurality of blocks in which each row of the unit matrix is shifted according to shift values from “

1”

to “

p−

1”

when performing decoding processing on the received data coded with low density parity check codes;

a second selector configured to further divide each of the groups into Y (Y is an integer equal to or greater than

     2) subgroups to output the subgroups;

a first memory configured to store a plurality of first variables for performing calculation processing on a probability β

in association with a first address;

a second memory configured to store a plurality of second variables for performing calculation processing on an external value α

in association with a second address;

a rotator configured to perform rotation processing with a rotation value corresponding to the shift value and the subgroup on the plurality of second variables stored in the second memory and transmits the plurality of second variables to an operation unit;

the operation unit comprising (p/Y) operation circuits configured to perform parallel operation processing using the first variable and the second variable in the subgroup units in conjunction with the shift value; and

a control section configured to control the first selector, the second selector and the rotator according to the shift value and the rotation value.

2. The error detection/correction circuit according to claim 1, wherein the control section controls the division into the subgroups based on lower addresses of the first address and the second address.

3. The error detection/correction circuit according to claim 1, wherein the control section performs control so that each of the groups is divided into two subgroups based on the least significant address bits of the first address and the second address.

4. A memory controller comprising:

a first selector configured to divide received data into p groups to output the groups based on a check matrix comprising a block made up of a unit matrix of a size p (p is an integer equal to or greater than

     8) and a plurality of blocks in which each row of the unit matrix is shifted according to shift values from “

1”

to “

p−

1”

when performing decoding processing on the received data coded with low density parity check codes;

a second selector configured to further divide each of the groups into Y (Y is an integer equal to or greater than

     2) subgroups to output the subgroups;

a first memory configured to store a plurality of first variables for performing calculation processing on a probability β

in association with a first address;

a second memory configured to store a plurality of second variables for performing calculation processing on an external value α

in association with a second address;

a rotator configured to perform rotation processing with a rotation value corresponding to the shift value and the subgroup on the plurality of second variables stored in the second memory and transmits the plurality of second variables to an operation unit;

the operation unit comprising (p/Y) operation circuits configured to perform parallel operation processing using the first variable and the second variable in the subgroup units in conjunction with the shift value; and

a control section configured to control the first selector, the second selector and the rotator according to the shift value and the rotation value.

5. The memory controller according to claim 4, wherein the control section controls the division into the subgroups based on lower addresses of the first address and the second address.

6. The memory controller according to claim 4, wherein the control section performs control so that each of the groups is divided into two subgroups based on the least significant address bits of the first address and the second address.

7. A semiconductor memory apparatus comprising:

a memory controller comprising an error detection/correction circuit comprising;

a first selector configured to divide received data into p groups to output the groups based on a check matrix comprising a block made up of a unit matrix of a size p (p is an integer equal to or greater than

     8) and a plurality of blocks in which each row of the unit matrix is shifted according to shift values from “

1”

to “

p−

1”

when performing decoding processing on the received data coded with low density parity check codes;

a second selector configured to further divide each of the groups into Y (Y is an integer equal to or greater than

     2) subgroups to output the subgroups;

a first memory configured to store a plurality of first variables for performing calculation processing on a probability β

in association with a first address;

a second memory configured to store a plurality of second variables for performing calculation processing on an external value α

in association with a second address;

a rotator configured to perform rotation processing with a rotation value corresponding to the shift value and the subgroup on the plurality of second variables stored in the second memory and transmits the plurality of second variables to an operation unit;

the operation unit comprising (p/Y) operation circuits configured to perform parallel operation processing using the first variable and the second variable in the subgroup units in conjunction with the shift value; and

a control section configured to control the first selector, the second selector and the rotator according to the shift value and the rotation value; and

a NAND-type flash memory section in which the memory controller reads and writes data.

8. The semiconductor memory apparatus according to claim 7, wherein the control section controls the division into the subgroups based on lower addresses of the first address and the second address.

9. The semiconductor memory apparatus according to claim 7, wherein the control section performs control so that each of the groups is divided into two subgroups based on the least significant address bits of the first address and the second address.

10. An error detection correction method comprising:

calculating a logarithmic likelihood ratio from a received signal when performing decoding processing on received data coded with low density parity check codes;

making a hard decision based on the logarithmic likelihood ratio or a probability β

;

making a parity check based on the hard decision result;

dividing the received signal into p (p is an integer equal to or greater than

     8) groups;

dividing each of the groups into Y (Y is an integer equal to or greater than

     2) subgroups;

storing a plurality of first variables of the subgroup for performing calculation processing on the probability β

in a first memory in association with a first address and storing a plurality of second variables of the subgroup for performing calculation processing on an external value α

in a second memory in association with a second address; and

performing selection processing on the plurality of first variables stored in the first memory;

performing rotation processing on the plurality of second variables stored in the second memory; and

performing parallel processing on the p/Y first variables subjected to selection processing and the p/Y second variables subjected to rotation processing through p/Y operation circuits,

wherein the low density parity check codes are based on a check matrix comprising a block made up of a unit matrix of a size p (p is an integer equal to or greater than

     8) and a plurality of blocks in which each row of the unit matrix is shifted according to shift values “

1”

to “

p−

1,” and

the groups correspond to the shift values and the rotation processing and the selection processing are executed based on rotation values according to the shift value and the subgroup.

11. The error detection correction method according to claim 10, wherein the subgroup division is performed based on lower addresses of the first address and the second address.

12. The error detection correction method according to claim 11, wherein the subgroup division is performed based on the least significant address bits of the first address and the second address.