THIN FILM TRANSISTOR, AND METHOD OF MANUFACTURING THE SAME

• US 20110240987A1
• Filed: 03/16/2011
• Published: 10/06/2011
• Est. Priority Date: 04/06/2010
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: LEE, Je-Hun, KIM, Joo-Han
• Granted Patent: US 8,952,376 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A thin film transistor and a method of manufacturing the same are provided. The thin film transistor includes a first gate electrode and an active layer including a crystalline oxide semiconductor which is insulated from the first gate electrode by a first insulating layer and the active layer is arranged to overlap the first gate electrode. A source electrode is formed including at least a portion overlaps the active layer, and a drain electrode is arranged being spaced apart from the source electrode and at least a portion of the drain electrode overlaps the active layer, wherein the source electrode and the drain electrode are insulated from the first gate electrode by the first insulating layer.

Claims

1. A thin film transistor, comprising:

a first gate electrode;

an active layer comprising a crystalline oxide semiconductor being insulated from the first gate electrode by a first insulating layer, the active layer being arranged to overlap the first gate electrode; and

a source electrode and a drain electrode spaced apart from the source electrode,

wherein the source electrode and the drain electrode are insulated from the first gate electrode by the first insulating layer, and

wherein at least a portion of the source electrode overlaps with the active layer, and at least a portion of the drain electrode overlaps with the active layer.

2. The thin film transistor of claim 1, wherein the active layer comprises a single layer of the crystalline oxide semiconductor.

3. The thin film transistor of claim 1, wherein the active layer comprises a double layer comprising an amorphous oxide semiconductor layer and a crystalline oxide semiconductor layer are laminated, and the crystalline oxide semiconductor layer is arranged adjacent to the first insulating layer.

4. The thin film transistor of claim 3, wherein the thickness of the amorphous oxide semiconductor layer exceeds the thickness of the crystalline oxide semiconductor layer.

5. The thin film transistor of claim 1, further comprising:

a second insulating layer; and

a second gate electrode, the second gate electrode and the first gate electrode being arranged on opposite sides of the active layer,

wherein the second gate electrode is insulated from the active layer by the second insulating layer.

6. The thin film transistor of claim 5, wherein the active layer comprises a triple layer comprising a first crystalline oxide semiconductor layer, an amorphous oxide semiconductor layer, and a second crystalline oxide semiconductor layer, and

wherein the first crystalline oxide semiconductor layer is arranged adjacent to the first insulating layer, and the second crystalline oxide semiconductor layer is arranged adjacent to the second insulating layer.

7. The thin film transistor of claim 6, wherein the thickness of the amorphous oxide semiconductor layer exceeds the thickness of the first crystalline oxide semiconductor layer or the thickness of the second crystalline oxide semiconductor layer.

8. The thin film transistor of claim 1, wherein the crystalline oxide semiconductor comprises an oxide material selected from one of Zn, In, Ga, Sn, Hf, or any combinations thereof.

9. The thin film transistor of claim 1, wherein an energy band gap of the crystalline oxide semiconductor exceeds an energy band gap of an amorphous oxide semiconductor.

10. The thin film transistor of claim 1, wherein a light absorption coefficient of the crystalline oxide semiconductor is smaller than a light absorption coefficient of an amorphous oxide semiconductor.

11. The thin film transistor of claim 1, wherein a charge mobility of the crystalline oxide semiconductor is lower than a charge mobility of an amorphous oxide semiconductor.

12. The thin film transistor of claim 1, wherein the degree of variation of a threshold voltage by light irradiation onto the crystalline oxide semiconductor is lower than the degree of variation of a threshold voltage by light irradiation onto an amorphous oxide semiconductor.

13. A method of manufacturing a thin film transistor, the method comprising:

forming a first gate electrode;

forming an active layer comprising crystalline oxide semiconductor being insulated from the first gate electrode by a first insulating layer and the active layer being arranged to overlap the first gate electrode; and

forming a source electrode and a drain electrode spaced apart from the source electrode,

wherein the source electrode and the drain electrode are insulated from the first gate electrode by the first insulating layer, and

wherein at least a portion of the source electrode overlaps with the active layer, and at least a portion of the drain electrode overlaps with the active layer.

14. The method of claim 13, wherein the forming the active layer comprises using a reactive sputtering method using argon gas and oxygen gas, and controls the degree of crystallization of the oxide semiconductor is controlled by adjusting a temperature and a partial pressure ratio of the argon gas to the oxygen gas.

15. The method of claim 13, wherein the forming the active layer comprises forming a single layer of the crystalline oxide semiconductor.

16. The method of claim 13, wherein the forming the active layer comprises forming a double layer in which an amorphous oxide semiconductor layer and a crystalline oxide semiconductor layer are laminated, and arranging the crystalline oxide semiconductor layer adjacent to the first insulating layer.

17. The method of claim 13, further comprising:

forming a second gate electrode on an opposite side to the first gate electrode through the active layer and the source electrode and the drain electrode being insulated from the active layer by the second insulating layer.

18. The method of claim 17, wherein the forming the active layer comprises forming a triple layer in which a first crystalline oxide semiconductor layer, an amorphous oxide semiconductor layer, and a second crystalline oxide semiconductor layer are laminated, arranging the first crystalline oxide semiconductor layer adjacent to the first insulating layer, and arranging the second crystalline oxide semiconductor layer adjacent to the second insulating layer.

19. The method of claim 16, wherein the forming of the crystalline oxide semiconductor layer and the amorphous oxide semiconductor layer is performed using a reactive sputtering method using argon gas and oxygen gas, wherein

a temperature at which the crystalline oxide semiconductor layer is formed is higher than a temperature at which the amorphous oxide semiconductor layer is formed, and

wherein a partial pressure ratio of the argon gas to the oxygen gas in forming the crystalline oxide semiconductor layer is lower than a partial pressure ratio of the argon gas to the oxygen gas in forming the amorphous oxide semiconductor layer.

20. The method of claim 18, wherein the forming of the first crystalline oxide semiconductor layer, the amorphous oxide semiconductor layer, and the second crystalline oxide semiconductor layer is performed using a reactive sputtering method using argon gas and oxygen gas, wherein

a temperature at which the first crystalline oxide semiconductor layer or the second crystalline oxide semiconductor layer is formed is higher than a temperature at which the amorphous oxide semiconductor layer is formed, and

wherein a partial pressure ratio of the argon gas to the oxygen gas in forming the first crystalline oxide semiconductor layer or the second crystalline oxide semiconductor layer is lower than a partial pressure ratio of the argon gas to the oxygen gas in forming the amorphous oxide semiconductor layer.