THIN-FILM TRANSISTOR, METHOD OF MANUFACTURING THE SAME, AND DISPLAY DEVICE

• US 20110240998A1
• Filed: 03/22/2011
• Published: 10/06/2011
• Est. Priority Date: 03/30/2010
• Status: Active Grant

• Current Assignee: JDI Design and Development GK
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Oshima, Yoshihiro, Morosawa, Narihiro
• Granted Patent: US 9,859,437 B2
• Time in Patent Office: Days
• US Class Current: 257/57
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

A thin film transistor is provided. The thin film transistor includes an oxide semiconductor layer including a source region, a drain region, and a channel region wherein a portion of the source and drain regions has an oxygen concentration less than the channel region. Further provided is a thin film transistor that includes an oxide semiconductor layer including a source region, a drain region, and a channel region, wherein a portion of the source and drain regions includes a dopant selected from the group consisting of aluminum, boron, gallium, indium, titanium, silicon, germanium, tin, lead, and combinations thereof.

Claims

1. A thin film transistor comprising an oxide semiconductor layer including a source region, a drain region, and a channel region wherein a portion of the source and drain regions has an oxygen concentration less than the channel region.

2. The thin film transistor of claim 1, wherein the portion of the source and drain regions is a low-resistance region extending in a depth direction from an upper face thereof.

3. The thin film transistor of claim 2, wherein the low-resistance region extends within 10 nm in the depth direction from the upper face thereof.

4. The thin film transistor of claim 1, further including a high-resistance material layer that is formed on at least the portion of the source and drain regions.

5. The thin film transistor of claim 4, wherein the high-resistance material layer is selected from the group consisting of titanium oxide, aluminum oxide, and indium oxide.

6. The thin film transistor of claim 4, wherein the high-resistance material layer includes a plurality of island-shaped metal films.

7. The thin film transistor of claim 6, wherein the island-shaped metal films are spaced apart so as to provide a clearance gap.

8. The thin film transistor of claim 7, wherein the portion of the source and drain regions is a low-resistance region extending in a depth direction from an upper face thereof, and wherein a first portion of the island-shaped metal films is in contact with the low resistance region and a second portion of the island-shaped metal films is in contact with a gate electrode.

9. The thin film transistor of claim 1, further including an insulating layer.

10. The thin film transistor of claim 1, further including a source electrode and a drain electrode.

11. The thin film transistor of claim 1, wherein the thin film transistor is configured as any one of a top gate structure and a bottom gate structure.

12. A thin film transistor comprising an oxide semiconductor layer including a source region, a drain region, and a channel region, wherein a portion of the source and drain regions includes a dopant selected from the group consisting of aluminum, boron, gallium, indium, titanium, silicon, germanium, tin, lead, and combinations thereof.

13. The thin film transistor of claim 12, wherein the portion of the source and drain regions is a low-resistance region extending in a depth direction from an upper face thereof.

14. The thin film transistor of claim 13, wherein the low-resistance region extends at least within 30 nm in the depth direction from the upper face thereof.

15. The thin film transistor of claim 12, further including a high-resistance material layer that is formed on at least the portion of the source and drain regions.

16. The thin film transistor of claim 15, wherein the high-resistance material layer includes a constituent selected from the group consisting of titanium, aluminum, and indium, boron, gallium, silicon, germanium, tin, and lead.

17. The thin film transistor of claim 15, wherein the high-resistance material layer includes any one of a plurality of island-shaped metal films and a plurality of island-shaped nonmetal films.

18. The thin film transistor of claim 17, wherein any one of the island-shaped metal films and the island-shaped nonmetal films are spaced apart so as to provide a clearance gap.

19. The thin film transistor of claim 18, wherein the portion of the source and drain regions is a low-resistance region extending in a depth direction from an upper face thereof, and wherein a first portion of any one of the island-shaped metal films and the island-shaped nonmetal films is in contact with the low resistance region and a second portion of any one of the island-shaped metal films and the island-shaped nonmetal films is in contact with a gate electrode.

20. The thin film transistor of claim 12, further including an insulating layer.

21. The thin film transistor of claim 12, further including a source electrode and a drain electrode.

22. The thin film transistor of claim 12, wherein the thin film transistor is configured as any one of a top gate structure and a bottom gate structure.