FLAT PANEL DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME

• US 20110241010A1
• Filed: 03/08/2011
• Published: 10/06/2011
• Est. Priority Date: 04/01/2010
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Mobile Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: PARK, Kyung-Min
• Granted Patent: US 8,610,126 B2
• Time in Patent Office: Days
• US Class Current: 257/71
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors

Abstract

Provided are a flat panel display device and a method of manufacturing the same. The flat panel display device includes a first thin-film transistor including a first active layer, a first insulation layer disposed on the first active layer, and a first gate electrode disposed on the first insulation layer; a second thin-film transistor including a second active layer, the first insulation layer disposed on the second active layer, a second insulation layer disposed on the first insulation layer, and a second gate electrode disposed on the second insulation layer, and electrically connected to the first thin-film transistor; and a capacitor electrically connected to the first thin-film transistor and the second thin-film transistor. In the structure as described above, since different numbers of insulation layers are interposed between active layers and gate electrode in each of the first thin-film transistor and the second thin-film transistor, threshold voltages of the first thin-film transistor and the second thin-film transistor are significantly different from each other, and thus it becomes easy to control the threshold voltages of the first thin-film transistor and the second thin-film transistor.

Claims

1. A flat panel display device comprising:

a first thin-film transistor comprising a first active layer, a first insulation layer disposed on the first active layer, and a first gate electrode disposed on the first insulation layer;

a second thin-film transistor comprising a second active layer, wherein the first insulation layer is disposed on the second active layer,

a second insulation layer disposed on the first insulation layer, and a second gate electrode disposed on the second insulation layer, and electrically connected to the first thin-film transistor; and

a capacitor electrically connected to the first thin-film transistor and the second thin-film transistor.

2. The flat panel display device of claim 1, wherein the second insulation layer extends onto the first gate electrode.

3. The flat panel display device of claim 1, wherein the capacitor comprises:

a first electrode disposed on the first insulation layer; and

a second electrode disposed over the second insulation layer,

wherein the second insulation layer is interposed between the first electrode and the second electrode.

4. The flat panel display device of claim 3, wherein the first gate electrode and the first electrode comprise the same material.

5. The flat panel display device of claim 3, wherein the second gate electrode and the second electrode comprise the same material.

6. The flat panel display device of claim 1, wherein the first active layer comprises:

a first channel region that overlaps the first gate electrode and contains a first type impurity; and

a first source region and a first drain region that are disposed on opposite sides of the first channel region and contain a second type impurity, wherein the polarity of the second type impurity is opposite to that of the first type impurity.

7. The flat panel display device of claim 6, wherein the first type impurity is an n-type impurity, and the second type impurity is a p-type impurity.

8. The flat panel display device of claim 1, wherein the second active layer comprises:

a second channel region that overlaps the second gate electrode and contains a second type impurity;

a second source region and a second drain region that are disposed on opposite sides of the second channel region and contain a first type impurity, wherein the polarity of the first type impurity is opposite to that of the second type impurity; and

regions with low impurity concentration that are disposed between the second channel region and the second source and drain regions and comprise the first type impurity at a concentration lower than that of the first impurity in the second source and drain regions.

9. The flat panel display device of claim 8, wherein the first type impurity is an n-type impurity, and

the second type impurity is a p-type impurity.

10. A method of forming a flat panel display device, the method comprising:

(a) forming a first active layer of a first thin-film transistor and a second active layer of a second thin-film transistor;

(b) forming a first insulation layer on the first active layer and the second active layer;

(c) forming a second insulation layer on the first insulation layer on the second active layer;

(d) forming a first gate electrode of the first thin-film transistor that faces the first active layer across the first insulation layer; and

(e) forming a second gate electrode of the second thin-film transistor that faces the second active layer across the first insulation layer and the second insulation layer.

11. The method of claim 10, wherein the second insulation layer extends over the first gate electrode.

12. The method of claim 10, further comprising implanting a first type impurity into the first active layer and the second active layer after the first insulation layer is formed.

13. The method of claim 12, further comprising implanting a second type impurity, wherein the polarity of the second type impurity is opposite to that of the first type impurity, into the entire second active layer and a portion of the first active layer not covered by the first gate electrode, after the first gate electrode is formed and before the second insulation layer and the second gate electrode are formed.

14. The method of claim 13, wherein the first type impurity is an n-type impurity, and

the second type impurity is a p-type impurity.

15. The method of claim 10, further comprising forming a first electrode of a capacitor between the first insulation layer and the second insulation layer using the same material used to form the first gate electrode.

16. The method of claim 10, further comprising forming a first electrode of a capacitor on the first insulation layer using the same material used to form the first gate electrode.

17. The method of claim 16, further comprising:

forming a metal layer on the second insulation layer;

forming a first photoresist layer on the metal layer;

patterning the first photoresist layer; and

forming the second gate electrode and a second electrode of the capacitor by patterning a portion of the metal layer exposed by the patterned first photoresist layer.

18. The method of claim 17, further comprising implanting a second type impurity into a portion of the first active layer not covered by the first gate electrode, before the first photoresist layer is patterned.

19. The method of claim 18, further comprising:

forming a second photoresist layer to cover the first thin-film transistor;

implanting a first type impurity into a portion corresponding to the second thin-film transistor which is covered by the first photoresist layer; and

removing the first and second photoresist layers, after the second gate electrode and the second electrode are formed.

20. The method of claim 19, further comprising forming regions with low impurity concentration in the second active layer by further implanting the first type impurity into a portion of the second active layer not covered by the second gate electrode, after the first and second photoresist layers are removed.