DOUBLE-SIDED INTEGRATED CIRCUIT CHIPS

• US 20110241082A1
• Filed: 06/20/2011
• Published: 10/06/2011
• Est. Priority Date: 05/16/2006
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Gambino, Jeffrey Peter, Jaffe, Mark David, Dalton, Timothy Joseph, Stamper, Anthony Kendall, Bernstein, Kerry, Luce, Stephen Ellinwood, Kartschoke, Paul David
• Granted Patent: US 8,421,126 B2
• Time in Patent Office: Days
• US Class Current: 257/255
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor structure and method of fabricating the structure. The method includes removing the backside silicon from two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers. Contacts are then formed in the upper wafer to devices in the lower wafer and wiring levels are formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided.

Claims

1. A semiconductor structure, comprising:

one or more first devices of a first substrate, said first substrate comprising a first oxide layer, a first silicon layer on said first oxide layer and a first lowermost dielectric layer on said first silicon layer;

one or more second devices of a second substrate, said second substrate comprising a second oxide layer, a second silicon layer on said second oxide layer and a second lowermost dielectric layer on said second silicon layer;

a top surface of said first oxide layer bonded to a top surface of said second oxide layer;

electrically conductive first contacts to said second devices, said first contacts extending from a top surface of said second lowermost dielectric layer through said second lowermost dielectric layer to said first devices;

electrically conductive second contacts to said first devices, said second contacts extending from said top surface of said second lowermost dielectric layer through said second lowermost dielectric layer, through said first and second oxide layers to those portions of said second devices formed in said second silicon layer; and

one or more second wiring levels over said second lowermost dielectric layer, each wiring level of said second wiring levels comprising electrically conductive wires in a corresponding dielectric layer, one or more wires of a lowermost wiring level of said second wiring levels in physical and electrical contact with said first and second contacts.

2. The structure of claim 1, further including:

one or more first wiring levels over said first silicon layer and interconnecting said first devices, each wiring level of said first wiring levels comprising electrically conductive wires in a corresponding dielectric layer, said one or more first wiring levels including electrically conductive wires formed in said first lowermost dielectric layer.

3. The structure of claim 2, further including:

electrically conductive third contacts, said third contacts extending from said top surface of said second lowermost dielectric layer through said second lowermost dielectric layer, through said first and second oxide layers and through said first silicon layer to one or more wires of said wires in said first lowermost dielectric layer, said third contacts electrically isolated from said first silicon layer.

4. The structure of claim 1, further including:

a handle substrate attached to an uppermost dielectric layer of said first substrate furthest away from said first silicon layer.

5. The structure of claim 1, further including:

said first and second devices aligned to each other.

6. The structure of claim 1, wherein said first devices are N-channel field effect transistors and said second devices are P-channel field effect transistors.

7. The structure of claim 1, wherein said first silicon layer is a single crystal silicon layer having a <

100>

crystal orientation, said first devices are N-channel field effect transistors and the channel length of said N-channel field effect transistors is along the [100] crystal direction of said first upper silicon layer and wherein said second silicon layer is a single crystal silicon layer having a <

110>

crystal orientation, said second devices are P-channel field effect transistors and the channel length of said P-channel field effect transistors is along the [110] crystal direction of said second upper silicon layer.

8. The structure of claim 1, wherein said first devices are N-channel field effect transistors, sources and drains thereof are in tension and said second devices are P-channel field effect transistors sources and drains thereof are in compression.

9. The structure of claim 1, wherein said first and second devices are field effect transistors, said first devices having a higher threshold voltage than said second devices or wherein said first and second devices are field effect transistors, said first devices having a thicker gate dielectric than said second devices.

10. A semiconductor structure, comprising:

one or more first devices of a first substrate, said first substrate comprising a first oxide layer, a first silicon layer on said first oxide layer and a first lowermost dielectric layer on said first silicon layer;

one or more second devices of a second substrate, said second substrate comprising a second oxide layer, a second silicon layer on said second oxide layer and a second lowermost dielectric layer on said second silicon layer;

an inter-substrate dielectric layer on top of said first oxide layer,

electrically conductive landing pads in said inter-substrate dielectric layer, said landing pads extending from a top surface of said inter-substrate dielectric layer, through said first oxide layer to those portions of said first devices formed in said first silicon layer;

a silicon oxide bonding layer on top of said inter-substrate dielectric layer, a top surface of said bonding layer bonded to a top surface of said second oxide layer;

electrically conductive first contacts extending from a top surface of said second lowermost dielectric layer through said second lowermost dielectric layer to said first devices;

electrically conductive second contacts extending from said top surface of said second lowermost dielectric layer through said second lowermost dielectric layer, through said second oxide layer, through said bonding layer to said landing pads; and

one or more second wiring levels over said second lowermost dielectric layer, each wiring level of said second wiring levels comprising electrically conductive wires in a corresponding dielectric layer, one or more wires of a lowermost wiring level of said second wiring levels in physical and electrical contact with said first and second contacts.

11. The structure of claim 10, further including:

one or more first wiring levels formed over said first silicon layer interconnecting said first devices, each wiring level of said first wiring levels comprising electrically conductive wires in a corresponding dielectric layer, said one or more first wiring levels including electrically conductive wires formed in said first lowermost dielectric layer.

12. The structure of claim 10, further including:

a handle substrate attached to an uppermost dielectric layer of said first substrate furthest away from said first silicon layer.

13. The structure of claim 10, further including:

said first substrate aligned to said second substrate.

14. The structure of claim 10, wherein said first devices are N-channel field effect transistors and said second devices are P-channel field effect transistors.

15. The structure of claim 10, wherein said first silicon layer is a single crystal silicon layer having a <

100>

crystal orientation, said first devices are N-channel field effect transistors and the channel length of said N-channel field effect transistors is along the crystal direction of said first upper silicon layer and wherein said second silicon layer is a single crystal silicon layer having a <

110>

crystal orientation, said second devices are P-channel field effect transistors and the channel length of said P-channel field effect transistors is along the [110] crystal direction of said second upper silicon layer.

16. The structure of claim 10, wherein said first devices are N-channel field effect transistors, sources and drains thereof are in tension and said second devices are P-channel field effect transistors sources and drains thereof are in compression.

17. The structure of claim 10, wherein said first and second devices are field effect transistors, said first devices having a higher threshold voltage than said second devices or wherein said first and second devices are field effect transistors, said first devices having a thicker gate dielectric than said second devices.

18. A semiconductor device, comprising:

one or more first devices of a first substrate, said first substrate comprising a first oxide layer, a first silicon layer on said first oxide layer and a first lowermost dielectric layer on said first silicon layer;

one or more second devices of a second substrate, said second substrate comprising a second buried oxide, a second silicon layer on said second oxide layer and a second lowermost dielectric layer on said second silicon layer;

a top surface of said first oxide layer bonded to a top surface of said second oxide layer;

first electrically conductive contacts to said second devices, said first contacts extending from a top surface of said second lowermost dielectric layer through said second lowermost dielectric layer to said first devices; and

second electrically conductive contacts to metal silicide layers on surfaces of regions of said first silicon layer forming portions of said first devices, said second contacts extending from a top surface of said second lowermost dielectric layer through said second lowermost dielectric layer and said first and second buried dielectric layers to said metal silicide layers.

19. The structure of claim 18, wherein said metal silicide layers comprise nickel silicide.

20. A semiconductor device, comprising:

one or more first devices of a first substrate, said first substrate comprising a first buried oxide, a first silicon layer on said first oxide layer a first lowermost dielectric layer on said first silicon layer;

one or more second devices of a second substrate, said second substrate comprising a second buried oxide, a second silicon layer on said second oxide layer and a second lowermost dielectric layer on said second silicon layer;

an inter-substrate dielectric layer on top of said first oxide layer,

an electrically conductive landing pad extending from a top surface of said inter-substrate dielectric layer, through said first oxide layer to metal silicide layers on those portions of said first devices formed in said first silicon layer;

a silicon oxide bonding layer on top of said inter-substrate dielectric layer, a top surface of said silicon oxide layer bonded to a top surface of said bonding layer to said surface of said second oxide layer;

electrically conductive first contacts extending from a top surface of said second lowermost dielectric layer through said second lowermost dielectric layer to said second devices; and

electrically conductive second contacts to said landing pads, said second contacts extending from said top surface of said second lowermost dielectric layer through said second oxide layer, through said bonding layer to said landing pads.

21. The structure of claim 20, wherein said metal silicide layer comprises nickel silicide.