ALUMINUM FUSES IN A SEMICONDUCTOR DEVICE COMPRISING METAL GATE ELECTRODE STRUCTURES

• US 20110241086A1
• Filed: 11/08/2010
• Published: 10/06/2011
• Est. Priority Date: 03/31/2010
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Hoentschel, Jan, Kurz, Andreas, Schwan, Christoph
• Granted Patent: US 8,564,089 B2
• Time in Patent Office: Days
• US Class Current: 257/288
• CPC Class Codes: H01L 23/5256 comprising fuses, i.e. connections having their state changed from conductive to non-conductive
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

In sophisticated semiconductor devices, electronic fuses may be provided on the basis of a replacement gate approach by using the aluminum material as an efficient metal for inducing electromigration in the electronic fuses. The electronic fuse may be formed on an isolation structure, thereby providing an efficient thermal decoupling of the electronic fuse from the semiconductor material and the substrate material, thereby enabling the provision of efficient electronic fuses in a bulk configuration, while avoiding incorporation of fuses into the metallization system.

Claims

1. A semiconductor device, comprising:

a transistor element comprising a gate electrode structure, said gate electrode structure comprising a gate insulation layer formed of a high-k gate dielectric material and a gate electrode formed of a metal-containing electrode material, said metal-containing electrode material comprising aluminum; and

an electronic fuse comprising said high-k dielectric material and said metal-containing electrode material.

2. The semiconductor device of claim 1, wherein said gate electrode structure is formed on a semiconductor region that is directly connected to a crystalline semiconductor material of a substrate of said semiconductor device.

3. The semiconductor device of claim 1, wherein said electronic fuse is formed on a device region of reduced heat conductivity.

4. The semiconductor device of claim 3, wherein said device region of reduced heat conductivity comprises an isolation region embedded in a semiconductor material.

5. The semiconductor device of claim 1, wherein said metal-containing electrode material in said electronic fuse comprises at least one non-aluminum material layer.

6. The semiconductor device of claim 5, wherein said at least one non-aluminum layer is formed on sidewalls of said electronic fuse so as to laterally confine said aluminum.

7. The semiconductor device of claim 5, wherein said high-k dielectric material is formed on dielectric sidewalls of said electronic fuse so as to laterally confine said metal-containing electrode material of said electronic fuse.

8. The semiconductor device of claim 5, wherein said at least one non-aluminum layer and said aluminum form a layer stack that extends between a sidewall spacer structure so as to directly connect to said sidewall spacer structure.

9. The semiconductor device of claim 1, wherein said metal-containing electrode material comprises a metal species for adjusting a work function of said gate electrode structure.

10. The semiconductor device of claim 9, wherein said metal species comprises lanthanum.

11. The semiconductor device of claim 5, wherein said at least one non-aluminum layer comprises a titanium nitride layer.

12. The semiconductor device of claim 1, wherein said gate electrode structure has a gate length of approximately 50 nm or less.

13. The semiconductor device of claim 1, further comprising a contact level comprising a dielectric material formed laterally adjacent to and above said electronic fuse and said gate electrode structure, wherein said contact level further comprises contact elements so as to connect to said gate electrode structure and said electronic fuse.

14. A semiconductor device, comprising:

an electronic fuse formed on an isolation region that is laterally embedded in a semiconductor layer, said electronic fuse comprising at least one conductive metal-containing non-aluminum layer and an aluminum layer formed on said at least one conductive metal-containing non-aluminum layer.

15. The semiconductor device of claim 14, further comprising a high-k dielectric material formed at least between said at least one conductive metal-containing non-aluminum layer and said isolation region.

16. The semiconductor device of claim 15, wherein at least one of said high-k dielectric material and said at least one conductive metal-containing non-aluminum layer comprises a work function metal species for adjusting a work function of a gate electrode structure of a transistor formed in and above said semiconductor layer.

17. The semiconductor device of claim 14, wherein said at least one conductive metal-containing non-aluminum layer has an internal stress level of 1 Giga Pascal (GPa) or higher.

18. A method of forming an electronic fuse of a semiconductor device, the method comprising:

forming a gate electrode structure above a first device region and a fuse body above a second device region by applying a common patterning sequence;

exposing a top surface of a semiconductor material of said gate electrode structure and said fuse body; and

replacing said semiconductor material with a metal-containing electrode material that comprises an aluminum layer.

19. The method of claim 18, wherein forming said gate electrode structure and said fuse body comprises forming a layer stack comprising a high-k dielectric material species.

20. The method of claim 18, wherein replacing said semiconductor material with a metal-containing electrode material comprises removing said semiconductor material via said exposed top surface, forming a high-k dielectric material in said gate electrode structure and said fuse body and forming said metal-containing electrode material above said high-k dielectric material.