SEMICONDUCTOR DEVICE WITH BURIED GATES AND METHOD FOR FABRICATING THE SAME

• US 20110241106A1
• Filed: 11/04/2010
• Published: 10/06/2011
• Est. Priority Date: 03/31/2010
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: LEE, Seung-Ryong, Ahn, Tae-Hang
• Granted Patent: US 9,048,218 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A semiconductor device includes a supplementary layer and a silicon layer stacked over a substrate, a trench penetrating the supplementary layer and the silicon layer and formed over the substrate, a gate insulation layer formed along a surface of the trench, and a buried gate formed over the gate insulation layer and filling a portion of the trench.

Claims

1. A semiconductor device, comprising:

a supplementary layer and a silicon layer stacked over a substrate;

a trench penetrating the supplementary layer and the silicon layer and formed in the substrate;

a gate insulation layer formed along a surface of the trench; and

a buried gate formed over the gate insulation layer and filling a portion of the trench.

2. The semiconductor device of claim 1, wherein the supplementary layer comprises a layer formed of one selected from the group consisting of silicon germanium (SiGe), silicon germanium carbide (SiGeC), and silicon carbide (SiC).

3. The semiconductor device of claim 1, wherein the supplementary layer comprises a layer formed of silicon germanium (SiGe), and germanium (Ge) content in the supplementary layer ranges from approximately 5% to approximately 30%.

4. The semiconductor device of claim 1, wherein the supplementary layer has a thickness ranging from approximately 50 Å

to approximately 500 Å

, and the silicon layer has a thickness ranging from approximately 100 Å

to approximately 500 Å

.

5. The semiconductor device of claim 1, further comprising:

a capping layer formed over the buried gate and filling a remaining portion of the trench.

6. The semiconductor device of claim 1, further comprising:

a junction region formed in the silicon layer and on both sides of the trench.

7. The semiconductor device of claim 6, wherein the buried gate is spaced apart from the junction region by at least the supplementary layer.

8. A method for fabricating a semiconductor device, comprising:

stacking a supplementary layer and a silicon layer over the substrate;

forming a trench by etching the silicon layer, the supplementary layer, and the substrate;

forming a gate insulation layer along a surface of the trench; and

forming a buried gate filling a portion of the trench over the gate insulation layer.

9. The method of claim 8, wherein the supplementary layer comprises a layer formed of one selected from the group consisting of silicon germanium (SiGe), silicon germanium carbide (SiGeC), and silicon carbide (SIC).

10. The method of claim 8, wherein the supplementary layer comprises a layer formed of silicon germanium (SiGe), and germanium (Ge) content in the supplementary layer ranges from approximately 5% to approximately 30%.

11. The method of claim 8, wherein the supplementary layer and the silicon layer are formed in in-situ.

12. The method of claim 8, further comprising:

performing a pre-treatment process over the substrate before the supplementary layer and the silicon layer are stacked.

13. The method of claim 8, wherein the supplementary layer has a thickness ranging from approximately 50 Å

to approximately 500 Å

, and the silicon layer has a thickness ranging from approximately 100 Å

to approximately 500 Å

.

14. The method of claim 8, further comprising:

forming a capping layer filling a remaining portion of the trench over the buried gate.

15. The method of claim 8, after the stacking of the silicon layer, further comprising:

forming a junction region in the silicon layer through an ion implantation, wherein the junction region is spaced apart from the buried gate by at least the supplementary layer.