Dual Gate LDMOS Device with Reduced Capacitance

• US 20110241113A1
• Filed: 03/31/2010
• Published: 10/06/2011
• Est. Priority Date: 03/31/2010
• Status: Abandoned Application

• Current Assignee: Volterra Semiconductor Corporation (Analog Devices, Inc.)
• Original Assignee: Volterra Semiconductor Corporation (Analog Devices, Inc.)
• Inventors: Zuniga, Marco A.
• Application Number:
  US12/752,077
• Publication Number:
  US 20110241113A1
• Time in Patent Office: Days
• US Class Current: 257/343
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66681 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors

Abstract

A transistor includes an n-well implanted in a substrate, a source region including a p-body region in the n-well, and a n+ region and a p+ region in the p-body region, a drain region including a n+ region, and a dual gate between the source region and the drain region. The dual gate includes a first gate on a side closer to the source region and a second gate on a side closer to the drain region, the first gate separated from the second gate by a pre-determined distance sufficient that a capacitance between the gate and the drain is at least 15% lower than a capacitance of a transistor of the same unit cell size and configuration excepting that the first gate and second gate abut.

Claims

1. A transistor comprising:

an n-well implanted in a substrate;

a source region including a p-body region in the n-well, and a n+ region and a p+ region in the p-body region;

a drain region including a n+ region; and

a dual gate between the source region and the drain region, the dual gate including a first gate on a side closer to the source region and a second gate on a side closer to the drain region, the first gate separated from the second gate by a pre-determined distance sufficient that a capacitance between the gate and the drain is at least 15% lower than a capacitance of a transistor of the same unit cell size and configuration excepting that the first gate and second gate abut.

2. The transistor of claim 1, wherein the pre-determined distance is less than 0.5 um.

3. The transistor of claim 1, wherein a capacitance between the gate and the drain is about 50% of overall drain capacitance and is at least 15% lower than the capacitance of the transistor of the same unit cell size and configuration excepting that the first gate and the second gate abut.

4. The transistor of claim 1, wherein the first gate includes a first gate oxide layer, and the second gate includes a second oxide gate layer that is thicker than the first gate oxide layer.

5. The transistor of claim 4, wherein the first gate oxide layer has a first thickness of less than about 100 Å

, and the second gate oxide layer has a second thickness of at least five times the first thickness.

6. The transistor of claim 4, wherein the first gate oxide layer partially overlaps the first n+ region and the p-body region.

7. The transistor of claim 4, wherein the second gate oxide layer partially overlaps the second n+ region and the n-doped shallow drain.

8. The transistor of claim 1, wherein the p-body region includes

a first implant region having a first depth, a first lateral spread and a first concentration of a p-type impurity, and

a second implant region having a second depth, a second lateral spread and a second concentration of the p-type impurity, wherein the second depth is less than the first depth, the second lateral spread is greater than the first lateral spread and the second concentration is greater than the first concentration, wherein the p+ region and n+ region abut the second implant region.

9. A transistor comprising:

an n-well implanted in a substrate;

a source region including a p-body region in the n-well, and a n+ region and a p+ region in the p-body region;

a drain region including a n+ region; and

a dual gate between the source region and the drain region, the dual gate including a first gate on a side closer to the source region and a second gate on a side closer to the drain region, the first gate separated from the second gate by a pre-determined distance, the first gate coupled to a first electrode that is held at a first voltage or floated during an off-state of the transistor and the second gate coupled to a second electrode that is floated or held at a different, second voltage during an on-state of the transistor.

10. The transistor of claim 9, wherein the first gate is coupled to a first electrode that is held at a first voltage during an off-state of the transistor.

11. The transistor of claim 10, wherein the second gate is coupled to a second electrode that held at a different, second voltage during an on-state of the transistor.

12. The transistor of claim 10, wherein the second gate is coupled to a second electrode that is floated during an on-state of the transistor.

13. The transistor of claim 9, wherein the first gate is coupled to a first electrode that is floated during an off-state of the transistor.

14. The transistor of claim 9, wherein a difference between the first voltage and the second voltage is sufficient that a capacitance between the gate and the drain is at least 15% lower than a capacitance of a transistor of the same configuration and unit cell size in which the same voltage is applied to the first gate and second gate during the off-state.

15. The transistor of claim 14, wherein a capacitance between the gate and the drain is about 50% of overall drain capacitance and 20% lower than a capacitance of a transistor of the same configuration and unit cell size in which the same voltage is applied to the first gate and second gate during the off-state.

16. The transistor of claim 10, wherein the voltage difference is substantially in the range 0-6 volts or tristate in an off state and 0 to 12 volts or tristate in on state.

17. The transistor of claim 9, wherein during the off-state the first gate is connected to ground and second voltage is about 0 to 6 volts.

18. The transistor of claim 9, wherein during the off-state the first voltage is about 0 and second voltage is about 0 to 2 volts or tristate.

19. The transistor of claim 9, wherein the pre-determined distance is less than 0.5 um.

20. The transistor of claim 19, wherein first voltage, second voltage and pre-determined distance are configured such that a capacitance between the gate and the drain is at least 25% lower than a capacitance of a transistor of the same configuration and unit cell size in which the first gate and second gate abut and operate at the same voltage.

21. The transistor of claim 9, wherein the second oxide gate layer is thicker than the first gate oxide layer.

22. The transistor of claim 21, wherein the first gate oxide layer has a first thickness of less than about 100 Å

, and the second gate oxide layer has a second thickness of at least five times the first thickness.

23. The transistor of claim 9, wherein the p-body region includes

a first implant region having a first depth, a first lateral spread and a first concentration of a p-type impurity, and

a second implant region having a second depth, a second lateral spread and a second concentration of the p-type impurity, wherein the second depth is less than the first depth, the second lateral spread is greater than the first lateral spread and the second concentration is greater than the first concentration, wherein the p+ region and n+ region abut the second implant region.

24. The transistor of claim 9, wherein a gate side edge of the p-body region is self-aligned with the source-side edge of the second gate.

25. The transistor of claim 9, further comprising a n-doped shallow drain implanted in the drain region.

26. The transistor of claim 25, wherein a gate side edge of the n-doped shallow drain is self-aligned with the drain-side edge of the first gate.