High Voltage Semiconductor Devices and Methods of Forming the Same

• US 20110241160A1
• Filed: 03/30/2010
• Published: 10/06/2011
• Est. Priority Date: 03/30/2010
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Kerber, Martin, Wahl, Uwe
• Granted Patent: US 8,410,575 B2
• Time in Patent Office: Days
• US Class Current: 257/528
• CPC Class Codes: H01L 23/5225 Shielding layers formed together with wiring layers
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/53223 Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53252 Additional layers associated with noble-metal layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53266 Additional layers associated with refractory-metal layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 27/08 including only semiconductor components of a single kind
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

High voltage semiconductor devices and methods of fabrication thereof are described. In one embodiment, a method of forming a semiconductor device includes forming first trenches in an insulating material. A trap region is formed in the insulating material by introducing an impurity into the first trenches. The first trenches are filled with a conductive material.

Claims

1. A method of fabricating a semiconductor device, the method comprising:

forming first trenches in an insulating material;

forming a trap region in the insulating material by introducing an impurity into the first trenches; and

filling the first trenches with a conductive material.

2. The method of claim 1, wherein forming first trenches comprises:

forming a second dielectric over a first dielectric, the first dielectric comprising a plurality of dielectric layers; and

forming first trenches in the second dielectric.

3. The method of claim 1, wherein forming first trenches comprises:

forming a second dielectric over a first dielectric, the first dielectric comprising a single dielectric layer; and

forming first trenches in the second dielectric.

4. The method of claim 1, further comprising:

forming second trenches in the insulating material, the second trenches being formed under the first trenches and being separated by a portion of the insulating material; and

filling the second trenches with the conductive material.

5. The method of claim 4, wherein the filled first trenches form a first coil of a transformer, and wherein the filled second trenches form a second coil of the transformer.

6. The method of claim 1, wherein the impurity comprises silicon, germanium, or carbon.

7. The method of claim 1, wherein the impurity comprises a material selected from the group consisting of boron, indium, gallium, phosphorus, arsenic, and antimony.

8. The method of claim 1, wherein the impurity comprises an inert gas.

9. The method of claim 1, wherein the impurity comprises a metal.

10. The method of claim 1, wherein introducing an impurity into the first trenches comprises implanting the impurity into the first trenches.

11. The method of claim 10, wherein implanting the impurity comprises:

implanting at a first rotation at a first tilt relative to the normal to the top surface of the second insulating layer; and

implanting at a second rotation at the first tilt relative to the normal to the top surface of the second insulating layer, wherein the first rotation and the second rotation are separated by about 180°

.

12. The method of claim 11, wherein implanting at the first rotation forms a first portion of the trap region adjacent a first bottom corner of the first trenches, wherein implanting at the second rotation forms a second portion of the trap region adjacent a second bottom corner of the first trenches, the second bottom corner being opposite to the first bottom corner.

13. The method of claim 10, wherein implanting the impurity further comprises:

implanting at a first rotation at a first tilt relative to the normal to the top surface of the second insulating layer;

implanting at a second rotation at the first tilt relative to the normal to the top surface of the second insulating layer;

implanting at a third rotation at the first tilt relative to the normal to the top surface of the second insulating layer; and

implanting at a fourth rotation at the first tilt relative to the normal to the top surface of the second insulating layer, wherein the first rotation and the second rotation are separated by about 90°

, wherein the second rotation and the third rotation are separated by about 90°

, and wherein the third rotation and the fourth rotation are separated by about 90°

.

14. The method of claim 1, wherein the trap region has a shape of a partial dumbbell.

15. A method of fabricating a semiconductor device, the method comprising:

forming a first coil over a substrate;

forming an insulating material above the first coil;

forming trenches in the insulating material;

forming trap regions in the insulating material by implanting an impurity into the trenches; and

forming a second coil in the insulating material by filling the trenches with a conductive material.

16. The method of claim 15, wherein forming the second coil further comprises forming a liner before filling the trenches with a conductive material.

17. The method of claim 15, wherein the trap regions are formed around the corners of the trenches in a partial dumbbell shape.

18. The method of claim 15, wherein implanting the impurity into the trenches comprises performing a four rotation tilted implantation.

19. The method of claim 15, wherein implanting the impurity into the trenches comprises performing a two rotation tilted implantation.

20. The method of claim 15, wherein the impurity comprises a material selected from the group consisting of carbon, silicon, germanium, boron, indium, gallium, phosphorus, arsenic, and antimony.

21. The method of claim 15, wherein the impurity comprises a metal selected from the group consisting of Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Au, and Zn.

22. The method of claim 15, wherein the impurity comprises an element selected from the group consisting of helium, hydrogen, deuterium, argon, xeon, and neon.

23. The method of claim 15, wherein the trap regions are formed within about 50 nm from bottom surfaces of the trenches.

24. A transformer comprising:

a first coil overlying a semiconductor substrate;

an insulation material disposed over the first coil;

a second coil disposed in the insulation material; and

a trap region comprising an impurity disposed under the second coil in the insulation material.

25. The transformer of claim 24, wherein the trap region extends about 50 nm from bottom surfaces of the second coil.

26. The transformer of claim 24, wherein the impurity comprises a material selected from the group consisting of carbon, silicon, germanium, boron, indium, gallium, phosphorus, arsenic, and antimony.

27. The transformer of claim 24, wherein the impurity comprises a metal selected from the group consisting of Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Au, and Zn.

28. The transformer of claim 24, wherein the second coil is disposed within trenches in the insulating material, and wherein the trap regions are disposed around bottom corners of the trenches.