Device and Method for Manufacturing a Device

• US 20110241197A1
• Filed: 04/01/2010
• Published: 10/06/2011
• Est. Priority Date: 04/01/2010
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Theuss, Horst
• Granted Patent: US 8,350,381 B2
• Time in Patent Office: Days
• US Class Current: 257/693
• CPC Class Codes: B81C 1/0023 Packaging together an electronic processing unit die and a micromechanical structure die MEMS packages B81B7/0032; MEMS packaging processes B81C1/00261
• CPC Class Codes: B81C 1/00238 Joining a substrate with an electronic processing unit and a substrate with a micromechanical structure
• CPC Class Codes: G01P 1/023 for acceleration measuring devices
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2225/1035 the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 24/96 the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/12044 OLED
• CPC Class Codes: H01L 2924/1305 Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13055 Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/1306 Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13062 Junction field-effect transistor [JFET]
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/1815 : Shape
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

A device includes a first semiconductor chip and a first encapsulant that encapsulates the first semiconductor chip and that includes a cavity. A carrier and an electrical component are mounted on the carrier. The carrier is arranged such that the electrical component is enclosed by the cavity.

Claims

1. A device, comprising:

a first semiconductor chip;

a first encapsulant encapsulating the first semiconductor chip and comprising a cavity;

a carrier; and

an electrical component mounted on the carrier, wherein the carrier is arranged such that the electrical component is enclosed by the cavity.

2. The device of claim 1, wherein the electrical component comprises a semiconductor chip.

3. The device of claim 1, wherein the electrical component comprises a micro electro mechanical system (MEMS).

4. The device of claim 1, wherein the electrical component comprises a power supply.

5. The device of claim 1, further comprising:

a second semiconductor chip arranged to operate with the first semiconductor chip and/or the electrical component; and

a second encapsulant encapsulating the second semiconductor chip.

6. The device of claim 5, wherein the first encapsulant comprises an electrical through connection to provide an electrical connection between an external application and the electrical component and/or the second semiconductor chip.

7. The device of claim 6, further comprising:

a first redistribution layer providing an electrical connection between an external application and the electrical through connection and/or the first semiconductor chip.

8. The device of claim 6, further comprising:

a second redistribution layer providing an electrical connection between the electrical through connection and the electrical component and/or the second semiconductor chip.

9. The device of claim 1, wherein the first encapsulant comprises an aperture.

10. The device of claim 1, wherein the cavity is sealed.

11. A method for manufacturing a device, the method comprising:

encapsulating a first semiconductor chip with a first encapsulant, wherein the first encapsulant comprises a cavity;

mounting an electrical component on a carrier; and

arranging the carrier such that the electrical component is enclosed by the cavity.

12. The method of claim 11, wherein the first encapsulant comprises a mold compound and the cavity is formed by means of a molding tool.

13. The method of claim 11, further comprising

providing an electrical through connection to provide an electrical connection through the first encapsulant.

14. The method of claim 13, further comprising encapsulating a second semiconductor chip with a second encapsulant.

15. The method of claim 14, further comprising:

providing a first redistribution layer to provide an electrical connection between an external application and the electrical through connection and/or the first semiconductor chip.

16. The method of claim 14, further comprising:

providing a second redistribution layer to provide an electrical connection between the electrical through connection and the electrical component and/or the second semiconductor chip.

17. The method of claim 11, further comprising:

mounting the first semiconductor chip on a support carrier before encapsulating the first semiconductor chip; and

removing the support carrier after encapsulating the first semiconductor chip.

18. The method of claim 11, further comprising:

providing an aperture in the first encapsulant.

19. A device, comprising:

a carrier;

an electrical component mounted on the carrier;

a first encapsulant comprising a cavity and an electrical contact, wherein the carrier is arranged such that the electrical component is enclosed by the cavity and an electrical connection between the electrical component and the electrical contact is established.

20. The device of claim 19, further comprising:

a first semiconductor chip encapsulated by the first encapsulant.

21. The device of claim 19, wherein the electrical contact comprises an electrical through connection to provide an electrical connection through the first encapsulant.

22. The device of claim 19, wherein the electrical component comprises a power supply or a semiconductor chip.

23. A method for manufacturing a device, the method comprising:

mounting an electrical component on a carrier;

providing an encapsulant comprising a cavity and an electrical contact; and

arranging the carrier such that the electrical component is enclosed by the cavity and an electrical connection between the electrical component and the electrical contact is established.

24. The method of claim 23, further comprising encapsulating a semiconductor chip with the encapsulant and thereby forming the cavity by means of a molding tool.

25. A device, comprising:

an encapsulant comprising a cavity and an electrical through connection;

a semiconductor chip encapsulated by the encapsulant; and

an electrical component having an electrical contact and arranged in the cavity, wherein an electrical connection between the electrical contact and the electrical through connection is established.