Display Controller, Method For Operating The Display Controller, And Display System Having The Display Controller

• US 20110242412A1
• Filed: 02/16/2011
• Published: 10/06/2011
• Est. Priority Date: 03/30/2010
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Dong Han, Roh, Jong Ho
• Granted Patent: US 8,963,798 B2
• Time in Patent Office: Days
• US Class Current: 348/500
• CPC Class Codes: G06F 3/1438 using more than one graphics controller
• CPC Class Codes: G06F 3/1446 display composed of modules, e.g. video walls
• CPC Class Codes: G09G 5/12 Synchronisation between the display unit and other units, e.g. other display units, video-disc players

Abstract

The display controller includes a decoder, a control circuit, and a video output logic circuit. The decoder is configured to decode a first display command and output a decoding signal and first synchronizing information indicating the first display command is received. The control circuit is configured to generate a first control signal based on second synchronizing information and the decoding signal. The second synchronizing information is output from a second display controller and indicates a second display command is received. The video output logic circuit is configured to send a part of video data stored in a video source and a plurality of first timing control signals for displaying the part of the video data on a display to the display based on the first control signal.

Claims

1. A display controller, comprising:

a decoder configured to decode a first display command and output a decoding signal and first synchronizing information indicating the first display command is received;

a control circuit configured to generate a first control signal based on second synchronizing information and the decoding signal, the second synchronizing information being output from a second display controller and indicating if a second display command is received; and

a video output logic circuit configured to send a part of video data stored in a video source and a plurality of first timing control signals for displaying the part of the video data on a display to the display based on the first control signal.

2. The display controller of claim 1, wherein the control circuit is configured to generate a second control signal according to a result of comparing a start time-point of a first signal among the plurality of first timing control signals with a start time-point of a second signal among a plurality of second timing control signals generated by the second display controller,

wherein the video output logic circuit is configured to control a start time-point of the first signal in response to the second control signal.

3. The display controller of claim 2, wherein each of the first signal and the second signal is one of a vertical synchronizing signal, a horizontal synchronizing signal, a data enable signal and a video clock signal.

4. A display system, comprising:

a first display controller configured to control an operation of a first display and output first synchronizing information indicating a first display command is received; and

a second display controller configured to control an operation of a second display and output second synchronizing information indicating a second display command is received,

wherein the first display controller is configured to output a plurality of first timing control signals for controlling an operation of the first display in response to the first display command and the second synchronizing information,

wherein the second display controller is configured to output a plurality of second timing control signals for controlling an operation of the second display in response to the second display command and the first synchronizing information.

5. The display system of claim 4, wherein

the plurality of first timing control signals comprise a first vertical synchronizing signal or a first horizontal synchronizing signal,

wherein the plurality of second timing control signals comprise a second vertical synchronizing signal or a second horizontal synchronizing signal,

wherein the first vertical synchronizing signal and the second vertical synchronizing signal are synchronized to each other, and the first horizontal synchronizing signal and the second horizontal synchronizing signal are synchronized to each other.

6. The display system of claim 4, wherein

the first display controller includes,

a first decoder configured to decode the first display command and output a first decoding signal and the first synchronizing information;

a first detector configured to detect the second synchronizing information;

a first signal generator configured to output a first control signal in response to the first decoding signal and an output signal of the first detector; and

a first video output logic circuit configured to output a first part of video data stored in a video source and the plurality of first timing control signals to the first display in response to the first control signal,

the second display controller includes,

a second decoder configured to decode the second display command and outputting a second decoding signal and the second synchronize information;

a second detector configured to detect the first synchronizing information;

a second signal generator configured to output a second control signal in response to the second decoding signal and an output signal of the second detector; and

a second video output logic circuit configured to output a second part of video data stored in the video source and the plurality of second timing control signals to the second display in response to the second control signal.

7. The display system of claim 6, wherein each of the first decoder and the second decoder is embodied in a Special Function Register (SFR).

8. The display system of claim 4, further comprising:

a video source configured to store the video data, the video data corresponding to a frame,

wherein the first display controller is configured to send the plurality of first timing control signals with the first part of the video data to the first display so as to display the first part of the video data as a frame on the first display,

wherein the second display controller is configured to send the plurality of second timing control signals with the second part of the video data to the second display so as to display the second part of the video data as a frame on the second display.

9. The display system of claim 8, wherein each of the first display controller and the second display controller is configured to compare a start time-point of a first signal among the plurality of first timing control signals with a start time-point of a second signal among the plurality of second timing control signals, and adjusts a start time-point of the first signal and a start time-point of the second signal, respectively, according to a comparison result.

10. The display system of claim 9, wherein each of the first signal and the second signal is one of a vertical synchronizing signal, a horizontal synchronizing signal, a data enable signal and a video clock signal.

11. The display system of claim 9, wherein

the first display controller includes:

a first detector configured to compare the start time-point of the first signal with the start time-point of the second signal and output a first detection signal;

a first video output logic circuit configured to control the a start time-point of the first signal in response to the first detection signal,

the second display controller includes,

a second detector configured to compare the start time-point of the first signal with the start time-point of the second signal and output a second detection signal, and

a second video output logic circuit configured to control the start time-point of the second signal in response to the second detection signal.

12. The display system of claim 11, wherein

the first detector includes,

a first counter configured to count till the start time-point of the first signal;

a second counter configured to count till the start time-point of the second signal; and

a first comparator configured to compare a count value of the first counter with a count value of the second counter and output the first detection signal corresponding to a comparison result,

the second detector includes,

a third counter configured to count till the start time-point of the second signal;

a fourth counter configured to count till the start time-point of the first signal; and

a second comparator configured to compare a count value of the third counter with a count value of the fourth counter and outputting the second detection signal corresponding to a comparison result.

13-14. -14. (canceled)

15. A display system, comprising:

a plurality of display controllers, each display controller configured to output synchronizing information and control operation of a corresponding display based on the synchronizing information output from at least one other of the display controllers.

16. The system of claim 15, wherein each display controller is configured to receive a respective display command, and each display controller is configured to control operation of the corresponding display based on the synchronizing information output from at least one other of the display controllers and the received display command.

17. The system of claim 16, wherein each display controller is configured to generate the synchronizing information in response to the received display command.

18. The system of claim 17, wherein the display controllers are configured to control operation of the corresponding displays such that display of video data on the corresponding displays is synchronized.

19. The system of claim 18, further comprising:

a video source configured to store the video data, and wherein

each display controller is configured to control operation of the corresponding display to display a part of the stored video data.

20. The system of claim 18, wherein each display controller is configured to synchronize at least one of a vertical synchronizing signal, a horizontal synchronizing signal, a data enable signal and a video clock signal.

21. The system of claim 17, wherein each display controller is configured to control operation of the corresponding display based on the synchronizing information output from at least one other of the display controllers and the generated synchronizing information.