RESISTIVE MEMORY AND METHOD FOR CONTROLLING OPERATIONS OF THE SAME

• US 20110242874A1
• Filed: 04/02/2010
• Published: 10/06/2011
• Est. Priority Date: 04/02/2010
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Chien, Wei-Chih, Lee, Feng-Ming, Chen, Yi-Chou
• Granted Patent: US 8,295,075 B2
• Time in Patent Office: Days
• US Class Current: 365/148
• CPC Class Codes: G11C 11/5614 using conductive bridging RAM [CBRAM] or programming metallization cells [PMC]
• CPC Class Codes: G11C 11/5685 using storage elements comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0011 comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2213/51 Structure including a barrier layer preventing or limiting migration, diffusion of ions or charges or formation of electrolytes near an electrode
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: H10N 70/245 the species being metal cations, e.g. programmable metallization cells
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8416 adapted for supplying ionic species
• CPC Class Codes: H10N 70/8833 Binary metal oxides, e.g. TaOx

Abstract

A resistive memory and a method for controlling operations of the resistive memory are provided. The resistive memory has a first memory layer, a second memory layer and a medium layer. Each of the first memory layer and the second memory layer is used to store data. The medium layer is formed between the first memory layer and the second memory layer. The method comprises at least a step of measuring a resistance between the first memory layer and the second memory layer, and determining which one of a first state, a second state and a third state is a state of the resistive memory according to the measured resistance.

Claims

1. A method for controlling operations of a resistive memory, the resistive memory having a first memory layer, a second memory layer and a medium layer formed between the first memory layer and the second memory layer, the method comprising at least a step of:

(a) measuring a resistance between the first memory layer and the second memory layer, and determining which one of a first state, a second state and a third state is a state of the resistive memory according to the measured resistance.

2. The method as claimed in claim 1, wherein the step (a) comprises:

measuring the resistance as a first resistance by applying a first voltage to the resistive memory;

determining that the state of the resistive memory is the first state when the first resistance is equal to a predetermined value;

when the first resistance is different from the predetermined value, measuring the resistance as a second resistance by applying a second voltage to the resistive memory; and

determining that the state of the resistive memory is the second state when the second resistance is equal to the first resistance, or determining that the state of the resistive memory is the third state when the second resistance is not equal to the first resistance.

3. The method as claimed in claim 2 further comprising:

reprogramming the resistive memory to be at the third state when the state of the resistive memory is determined as the third state.

4. The method as claimed in claim 2, wherein the first voltage is less than the second voltage.

5. The method as claimed in claim 1, wherein each of the first memory layer and the second memory layer is a solid electrolyte, and the medium layer is an oxidizable electrode.

6. The method as claimed in claim 5, wherein the solid electrolyte is made of transition metal oxide.

7. The method as claimed in claim 5, wherein the solid electrolyte is made of materials containing at least one chalcogenide element.

8. The method as claimed in claim 5, wherein the oxidizable electrode is made of a material selected from a group consisting of silver, copper, and zinc.

9. The method as claimed in claim 1, wherein the resistive memory further comprises a first barrier layer and a second barrier layer, the first memory layer is an interface between the medium layer and the first barrier layer, and the second memory layer is an interface between the medium layer and the second barrier layer.

10. The method as claimed in claim 9, wherein the first barrier layer and the second barrier layer are made of a material selected from a group consisting of titanium nitride (TiN), tantalum nitride (TaN), platinum (Pt), and gold (Au).

11. The method as claimed in claim 9, wherein the medium layer is made of a material selected from a group consisting of tungsten oxide (WO), titanium oxide (TiO), nickel oxide (NiO), aluminum oxide (AlO), cupric oxide (CuO), zirconium oxide (ZrO), niobium oxide (NbO), and tantalum oxide (TaO).

12. A resistive memory, comprising:

a first solid electrolyte;

a second solid electrolyte; and

an oxidizable electrode, formed between the first solid electrolyte and the second solid electrolyte;

wherein the first solid electrolyte and the second solid electrolyte are made of transition metal oxide or materials containing at least one chalcogenide element.

13. The resistive memory as claimed in claim 12, wherein the oxidizable electrode is made of a material selected from a group consisting of silver, copper, and zinc.

14. The resistive memory as claimed in claim 12 further comprising a composing layer having two silicon oxide spacers and a tungsten layer, wherein the tungsten layer is formed between the two silicon oxide spacers, and the second solid electrolyte is formed between the oxidizable electrode and the composing layer.

15. The resistive memory as claimed in claim 14 further comprising a titanium nitride layer, an inter-metal dielectric (IMD) layer, and a substrate, wherein the titanium nitride layer is formed between the composing layer and the IMD layer, and the IMD layer is formed between the titanium nitride layer and the substrate.

16. A resistive memory, comprising:

a first barrier layer;

a second barrier layer; and

a metal oxide layer, formed between the first barrier layer and the second barrier layer;

wherein a first active region is between the first barrier layer and the metal oxide layer, and a second active region is between the second barrier layer and the metal oxide layer.

17. The resistive memory as claimed in claim 16, wherein the first barrier layer and the second barrier layer are made of a material selected from a group consisting of titanium nitride (TiN), tantalum nitride (TaN), platinum (Pt), and gold (Au), and the metal oxide layer is made of a material selected from a group consisting of tungsten oxide, titanium oxide, nickel oxide, aluminum oxide, cupric oxide, zirconium oxide, niobium oxide, and tantalum oxide.

18. The resistive memory as claimed in claim 16, wherein each of the first active region and the second active region has two resistive states.

19. The resistive memory as claimed in claim 16 further comprising two silicon oxide spacers, a first electrode, a second electrode, an inter-metal dielectric (IMD) layer, and a substrate, wherein the two silicon oxide spacers are contacted with the metal oxide layer and formed between the first barrier layer and the second barrier layer, the first electrode is formed on the first barrier layer, the second electrode is formed between the second barrier layer and the IMD layer, and the IMD layer is fothied between the second electrode and the substrate.

20. The resistive memory as claimed in claim 19, wherein the first electrode and the second electrode are made of aluminum-copper alloy.

21. A memory device, comprising:

a first memory layer having M resistive states, M being larger than or equal to 3;

a second memory layer having N resistive states; and

a medium layer formed between the first and second memory layers, wherein at least (M+N−

1) resistive states of the memory device are distinguishable according to a resistance between the first memory layer and second memory layer.