USING VARIABLE LENGTH PACKETS TO EMBED EXTRA NETWORK CONTROL INFORMATION

• US 20110243154A1
• Filed: 03/30/2010
• Published: 10/06/2011
• Est. Priority Date: 03/30/2010
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Valk, Kenneth Michael, Flynn, William Thomas, Shedivy, David Alan
• Granted Patent: US 8,514,885 B2
• Time in Patent Office: Days
• US Class Current: 370/471
• CPC Class Codes: H03M 13/09 Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
• CPC Class Codes: H04L 1/0072 Error control for data other than payload data, e.g. control data
• CPC Class Codes: H04L 1/0079 Formats for control data H04L1/16 takes precedence; training sequences H04L25/00 and H04L27/00

Abstract

A method and circuit for implementing variable length packets to embed extra control information in an interconnect system, and a design structure on which the subject circuit resides are provided. Packets are defined to include an End-to-End (ETE) Flow Unit within packet (Flit) count field in the packet header. The packet header also includes its own CRC field. When a nonzero ETE flit count field is received in an incoming packet from an incoming link, the specified number of embedded ETE flits is removed from the packet and is used the same as if the control information arrived in its own packet.

Claims

1. A method for implementing variable length packets to embed extra control information in an interconnect system comprising:

defining packets to include an End-to-End (ETE) Flow Unit within packet (Flit) count field in a packet header;

receiving an incoming packet from an incoming link;

checking said ETE flit count field, and responsive to an identified nonzero value in said ETE flit count field, removing a specified number of embedded ETE flits from the packet; and

using control information from said removed embedded ETE flits.

2. The method as recited in claim 1 includes sending an ETE cyclic redundancy check (CRC) flit with said embedded ETE flits, ETE CRC flit covers only said embedded ETE flits.

3. The method as recited in claim 1 includes identifying an ETE cyclic redundancy check (CRC) flit, and validating said embedded ETE flits responsive to a correct ETE CRC flit.

4. The method as recited in claim 1 includes determining when to embed ETE flits based upon predetermined configuration settings and available ETE messages in an outgoing ETE buffer.

5. The method as recited in claim 4 wherein said predetermined configuration settings include a maximum flits allowed to be embedded for each packet type.

6. The method as recited in claim 4 wherein said predetermined configuration settings include whether embedded flits include a cyclic redundancy check (CRC).

7. The method as recited in claim 1 includes creating said packet header including a header cyclic redundancy check (CRC) for transmitting on an outgoing link.

8. The method as recited in claim 7 includes removing a number of ETE messages from an ETE buffer corresponding to said nonzero value in said ETE flit count field, converting said ETE messages to ETE flits, and inserting said ETE flits into the packet after said packet header.

9. The method as recited in claim 8 includes inserting an ETE cyclic redundancy check (CRC) flit with said embedded ETE flits, ETE CRC flit covers only said embedded ETE flits.

10. The method as recited in claim 1 includes checking a packet header cyclic redundancy check (CRC), and discarding said embedded ETE flits responsive to an incorrect packet header CRC.

11. A circuit for implementing variable length packets to embed extra control information in an interconnect system comprising:

an interconnect link send circuit transferring an outgoing packet onto an outgoing link, said interconnect link send circuit building a packet header;

creating an End-to-End (ETE) Flow Unit within packet (Flit) count field in said packet header;

converting ETE messages into ETE flits, and embedding ETE flits into the outgoing packet after the packet header; and

an interconnect link receive circuit receiving an incoming packet from an incoming link;

checking said ETE flit count field, and responsive to an identified nonzero value in said ETE flit count field, removing a specified number of embedded ETE flits from the packet; and

using control information from said removed embedded ETE flits.

12. The circuit as recited in claim 11 wherein said interconnect link send circuit creating said packet header includes generating a header cyclic redundancy check (CRC) for said packet header.

13. The circuit as recited in claim 12 wherein said interconnect link receive circuit checks said packet header cyclic redundancy check (CRC), and discarding said embedded ETE flits responsive to an incorrect packet header CRC.

14. The circuit as recited in claim 11 wherein said interconnect link send circuit generates an ETE cyclic redundancy check (CRC) for said embedded ETE flits, and inserts said ETE CRC flit flits into the outgoing packet after said embedded ETE flits.

15. The circuit as recited in claim 11 wherein said interconnect link receive circuit identifies said ETE cyclic redundancy check (CRC) flit, and validating said embedded ETE flits responsive to a correct ETE CRC flit.

16. The circuit as recited in claim 11 wherein said interconnect link send circuit determines when to embed ETE flits based upon predetermined configuration settings and available ETE messages in an outgoing ETE buffer.

17. A multiple-path local rack interconnect system comprising:

a plurality of interconnect chips;

a plurality of serial links connected between each of said plurality of interconnect chips;

each of said interconnect chips including a circuit for implementing variable length packets to embed extra control information, said circuit comprising;

an interconnect link send circuit transferring an outgoing packet onto an outgoing link, said interconnect link send circuit building a packet header;

creating an End-to-End (ETE) Flow Unit within packet (Flit) count field in said packet header;

converting ETE messages into ETE flits, and embedding ETE flits into the outgoing packet after the packet header; and

an interconnect link receive circuit receiving an incoming packet from an incoming link;

checking said ETE flit count field, and responsive to an identified nonzero value in said ETE flit count field, removing a specified number of embedded ETE flits from the packet; and

using control information from said removed embedded ETE flits.

18. The multiple-path local rack interconnect system as recited in claim 17 wherein said interconnect link send circuit generates an ETE cyclic redundancy check (CRC) for said embedded ETE flits, and inserts said ETE CRC flit flits into the outgoing packet after said embedded ETE flits.

19. The multiple-path local rack interconnect system as recited in claim 18 wherein said interconnect link receive circuit identifies said ETE cyclic redundancy check (CRC) flit, and validating said embedded ETE flits responsive to a correct ETE CRC flit.

20. A design structure embodied in a machine readable medium used in a design process, the design structure comprising:

a circuit tangibly embodied in the machine readable medium used in the design process, said circuit for implementing variable length packets to embed extra control information, said circuit comprising;

an interconnect link send circuit transferring an outgoing packet onto an outgoing link, said interconnect link send circuit building a packet header;

creating an End-to-End (ETE) Flow Unit within packet (Flit) count field in said packet header;

converting ETE messages into ETE flits, and embedding ETE flits into the outgoing packet after the packet header; and

an interconnect link receive circuit receiving an incoming packet from an incoming link;

checking said ETE flit count field, and responsive to an identified nonzero value in said ETE flit count field, removing a specified number of embedded ETE flits from the packet; and

using control information from said removed embedded ETE flits, wherein the design structure, when read and used in the manufacture of a semiconductor chip produces a chip comprising said circuit.

21. The design structure of claim 20, wherein the design structure comprises a netlist, which describes said circuit.

22. The design structure of claim 20, wherein the design structure resides on storage medium as a data format used for the exchange of layout data of integrated circuits.

23. The design structure of claim 20, wherein the design structure includes at least one of test data files, characterization data, verification data, or design specifications.

24. The design structure of claim 20, wherein said interconnect link receive circuit checks an ETE cyclic redundancy check (CRC) flit for said embedded ETE flits, and validates said embedded ETE flits responsive to a correct ETE CRC flit.