SYNCHRONOUS TRANSFER OF STREAMING DATA IN A DISTRIBUTED ANTENNA SYSTEM
First Claim
1. A method of generating a jitter reduced clock signal from a serial encoded binary data stream transmitted over a communication medium, the method comprising:
- receiving a modulated signal that includes the encoded binary data stream via high speed data interface circuitry;
extracting the encoded binary data stream from the modulated signal;
generating a recovered clock signal that is phase locked to the encoded binary data stream with a phase-locked loop;
generating an error signal based on a difference between a phase of the encoded binary data stream and the recovered clock signal;
integrating the error signal with a loop filter configured with a bandwidth that allows the jitter and drift in the encoded binary data stream to generate a signal to control a voltage controlled oscillator;
generating a stable recovered clock signal by filtering the recovered clock signal to remove jitter without substantially affecting the frequency of the stable recovered clock signal to allow the stable recovered clock signal to track drift of the encoded binary data stream; and
producing at least one output clock by scaling the stable recovered clock signal frequency.
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Accused Products
Abstract
Embodiments of the invention provide a method, distributed antenna system, and components that generate a jitter reduced clock signal from a serial encoded binary data stream transmitted over a communication medium. The method comprises receiving a modulated signal that includes the encoded binary data stream and extracting the encoded binary data stream. The method further comprises generating a recovered clock signal that is phase locked to the encoded binary data stream, generating an error signal based on a difference between a phase of the encoded binary data stream and the recovered clock signal, and integrating the error signal to generate a signal to control a voltage controlled oscillator. The method further comprises generating a stable recovered clock signal and producing at least one output clock by scaling the stable recovered clock signal frequency.
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Citations
28 Claims
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1. A method of generating a jitter reduced clock signal from a serial encoded binary data stream transmitted over a communication medium, the method comprising:
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receiving a modulated signal that includes the encoded binary data stream via high speed data interface circuitry; extracting the encoded binary data stream from the modulated signal; generating a recovered clock signal that is phase locked to the encoded binary data stream with a phase-locked loop; generating an error signal based on a difference between a phase of the encoded binary data stream and the recovered clock signal; integrating the error signal with a loop filter configured with a bandwidth that allows the jitter and drift in the encoded binary data stream to generate a signal to control a voltage controlled oscillator; generating a stable recovered clock signal by filtering the recovered clock signal to remove jitter without substantially affecting the frequency of the stable recovered clock signal to allow the stable recovered clock signal to track drift of the encoded binary data stream; and producing at least one output clock by scaling the stable recovered clock signal frequency. - View Dependent Claims (2, 3, 4)
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5. A remote unit for a distributed antenna system, comprising:
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high speed data interface circuitry for communicating with a master unit; RF transceiver circuitry for communicating with a subscriber unit; a processing unit that multiplexes and routes data to the high speed data interface and that de-multiplexes and routes data from the high speed data interface circuitry to the RF transceiver circuitry; a clock recovery circuit that includes a phase-locked loop, the phase-locked loop including a loop filter having a bandwidth that does not substantially block the jitter or long-term drift in a modulated signal, the clock recovery circuit configured to receive the modulated signal from the high speed data interface circuitry that includes a serial encoded binary data stream and further configured to generate a recovered clock signal therefrom; a filtering circuit configured to filter the recovered clock signal to remove jitter without removing long-term drift in the modulated signal to generate a stable recovered clock signal; and a scaling circuit configured to scale the frequency of the stable recovered clock signal to generate at least one output signal at a respective predetermined target frequency. - View Dependent Claims (6, 7, 8, 9, 10, 11)
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12. A distributed antenna system, comprising:
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a master unit that clocks an encoded data stream onto high speed data interface circuitry via a modulated signal based upon an output of a reference oscillator; and at least one remote unit that receives the modulated signal from the master unit, each remote unit including; high speed data interface circuitry for receiving the modulated signal from the master unit, a clock recovery circuit that includes a phase-locked loop, the phase-locked loop in turn including a loop filter configured with a bandwidth that does not substantially block the jitter or long-term drift in the modulated signal, the clock recovery circuit configured to generate a recovered clock signal from the modulated signal that includes the encoded data stream; a filtering circuit configured to filter the recovered clock signal to remove jitter without removing long-term drift in the modulated signal and further configured to generate a stable recovered clock signal; and a scaling circuit configured to scale the frequency of the stabled recovered clock signal to generate an output signal at a predetermined target frequency. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20, 21)
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22. A method of generating a jitter reduced clock signal from an encoded data stream, the method comprising:
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generating a recovered clock signal based on the encoded data stream, the recovered clock signal being phase locked to an oscillator used to clock the encoded data stream onto a modulated signal; clocking data from the encoded data stream into a processing unit based on the recovered clock signal; detecting a periodic signal component, other than the bit rate, of the encoded data stream with the processing unit; generating a reference clock signal based on the detected periodic signal component; filtering the reference clock signal with a circuit having a bandwidth that substantially blocks jitter while substantially allowing long term drift of the reference clock signal; and scaling a frequency of the reference clock signal to generate at least one output signal at a predetermined target frequency.
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23. A master unit for a distributed antenna system, comprising:
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high speed data interface circuitry for exchange of data with at least one remote unit; first RF transceiver circuitry for communicating with at least one base transceiver system; a processing unit that multiplexes data from the at least one secondary interface, the first RF transceiver, and the second RF transceiver and routes the multiplexed data to a PHY for transmission via the high speed data interface circuitry, and that de-multiplexes data from the high speed data interface circuitry and routes the de-multiplexed data to at least one of the at least one secondary interface, the first RF transceiver, or the second RF transceiver; and a reference oscillator that is used to multiplex and/or de-multiplex the data to and/or from the high speed data interface. - View Dependent Claims (24, 25, 26, 27, 28)
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Specification