APPARATUS AND METHOD FOR HAZE CONTROL IN A SEMICONDUCTOR PROCESS

• US 20110244395A1
• Filed: 04/06/2010
• Published: 10/06/2011
• Est. Priority Date: 04/06/2010
• Status: Abandoned Application

• Current Assignee: Nanya Technology Corporation
• Original Assignee: Nanya Technology Corporation
• Inventors: Wang, Yi-Ming, Huang, Pei-Lin, Huang, Chun-Yen
• Application Number:
  US12/754,613
• Publication Number:
  US 20110244395A1
• Time in Patent Office: Days
• US Class Current: 430/319
• CPC Class Codes: G03F 1/38 Masks having auxiliary features, e.g. special coatings or marks for alignment or testing; Preparation thereof
• CPC Class Codes: G03F 7/70916 Pollution mitigation, i.e. mitigating effect of contamination or debris, e.g. foil traps

Abstract

A method for haze control in a semiconductor process, includes: providing an exposure tool with a photocatalyzer coating inside and exposing a wafer in the exposure tool in the presence of activation of the photocatalyzer coating. The photocatalyzer coating may be formed within an opaque region of a reticle.

Claims

1. A method for haze control in a semiconductor process, comprising:

providing an exposure tool with a photocatalyzer coating inside; and

exposing a wafer in the exposure tool in the presence of activation of the photocatalyzer coating.

2. The method for haze control in a semiconductor process of claim 1, wherein the exposure tool comprises a reticle, and the photocatalyzer coating is coated on the reticle.

3. The method for haze control in a semiconductor process of claim 2, wherein the reticle comprises:

a quartz-containing substrate;

a circuit pattern region disposed on the quartz-containing substrate; and

an opaque region surrounding the circuit pattern region, wherein the photocatalyzer coating is disposed within the opaque region.

4. The method for haze control in a semiconductor process of claim 3, wherein the photocatalyzer coating completely covers the opaque region.

5. The method for haze control in a semiconductor process of claim 3, wherein the reticle further comprises a reticle alignment mark near an edge of the reticle.

6. The method for haze control in a semiconductor process of claim 1, wherein the photocatalyzer coating is made of material selected from the group consisting of TiO₂, ZnO, SnO₂, ZrO₂, CdS, and ZnS.

7. An apparatus for haze control in a semiconductor process, comprising:

a substrate;

a circuit pattern region disposed on the substrate; and

a photocatalyzer coating disposed on the substrate.

8. The apparatus for haze control in a semiconductor process of claim 7 further comprising an opaque region surrounding the circuit pattern region, wherein the photocatalyzer coating is disposed within the opaque region.

9. The apparatus for haze control in a semiconductor process of claim 8, wherein the photocatalyzer coating completely covers the opaque region.

10. The apparatus for haze control in a semiconductor process of claim 7 further comprising a reticle alignment mark disposed near an edge of the substrate.

11. The apparatus for haze control in a semiconductor process of claim 7, wherein the photocatalyzer coating is made of material selected from the group consisting of TiO₂, ZnO, SnO₂, ZrO₂, CdS, and ZnS.

12. The apparatus for haze control in a semiconductor process of claim 7, wherein the photocatalyzer coating is made of TiO₂ with anatase phase.