Shielded Gate Trench FET with an Inter-electrode Dielectric Having a Low-k Dielectric Therein

• US 20110244641A1
• Filed: 04/08/2011
• Published: 10/06/2011
• Est. Priority Date: 07/09/2008
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: James J. Murphy, James Pan
• Inventors: Murphy, James J., Pan, James
• Granted Patent: US 8,329,538 B2
• Time in Patent Office: Days
• US Class Current: 438/270
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/51 Insulating materials associated therewith for MIS structures on thin film semiconductor H01L29/4908
• CPC Class Codes: H01L 29/512 the variation being parallel to the channel plane
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A method for forming a shielded gate trench field effect transistor (FET) includes forming trenches in a semiconductor region, forming a shield electrode in a bottom portion of each trench, and forming an inter-electrode dielectric (IED) extending over the shield electrode. The IED may comprise a low-k dielectric. The method also includes forming a gate electrode in an upper portion of each trench over the IED.

Claims

1-30. -30. (canceled)

31. A method for forming a shielded gate trench field effect transistor (FET), the method comprising:

forming trenches in a semiconductor region;

forming a shield electrode in a bottom portion of each trench;

forming an inter-electrode dielectric (IED) extending over the shield electrode, the IED comprising a low-k dielectric; and

forming a gate electrode in an upper portion of each trench over the IED.

32. The method of claim 31 wherein the IED comprises a high-k dielectric, the high-k dielectric extending between the low-k dielectric and the gate electrode.

33. The method of claim 31 wherein the gate electrode comprises metal.

34. The method of claim 31 further comprising:

forming a gate dielectric lining upper trench sidewalls; and

forming a conductive liner extending between the gate electrode and the gate dielectric.

35. The method of claim 31 wherein forming the IED further comprises forming an insulating material in a central portion of the IED such that the low-k dielectric extends along sides and bottom of the insulating material.

36. The method of claim 35 wherein the insulating material comprises an undoped oxide.

37. The method of claim 31 further comprising:

forming a gate dielectric lining upper trench sidewalls, the gate dielectric comprising a high-k dielectric.

38. The method of claim 37 wherein the high-k dielectric comprises oxide, and a concentration of the oxide is graded along a thickness of the high-k dielectric, the concentration of the oxide being highest in a portion of the high-k dielectric nearest the semiconductor region.

39. The method of claim 37 wherein the high-k dielectric further extends along a bottom of the gate electrode.

40. The method of claim 37 wherein the gate dielectric further comprises thermal oxide.

41. The method of claim 31 wherein the semiconductor region includes an epitaxial layer extending over a substrate, the method further comprising:

prior to forming the IED, forming a body region of a second conductivity type extending in the epitaxial layer;

prior to forming the IED, forming source regions of the first conductivity type adjacent to each trench in the body region; and

forming a conductor layer extending over the semiconductor region, the conductor layer contacting the source regions and being isolated from the gate electrode by a dielectric cap.

42. The method of claim 41 further comprising:

forming a dielectric liner extending between the gate electrode and the dielectric cap, the dielectric liner comprising nitride.