Implementing Control Using A Single Path In A Multiple Path Interconnect System

• US 20110246692A1
• Filed: 03/31/2010
• Published: 10/06/2011
• Est. Priority Date: 03/31/2010
• Status: Abandoned Application

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Walk, Bruce M., Valk, Kenneth M.
• Application Number:
  US12/751,469
• Publication Number:
  US 20110246692A1
• Time in Patent Office: Days
• US Class Current: 710/110
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: H04L 45/304 Route determination for signalling traffic

Abstract

A method and circuit for implementing control using a single path in a multiple path interconnect system, and a design structure on which the subject circuit resides are provided. Control TL messages include control information to be transferred between a respective source transport layer of a source interconnect chip and a destination transport layer of a destination interconnect chip. Each transport layer (TL) includes a TL message port identifying a port used to send and receive control TL messages for a pair of source TL and destination TL. The respective TL message port of the pair of source TL and destination TL defines the single path used for control messages.

Claims

1. A method for implementing control using a single path in a multiple path interconnect system comprising:

providing a transport layer (TL) with each source interconnect chip and each destination interconnect chip;

providing a control TL message to transfer control information between a respective pair of a source transport layer (TL) with a source interconnect chip and a destination transport layer (TL) of a destination interconnect chip; and

providing a respective TL message port identifying a port used to send and receive the control TL message for said source TL and said destination TL;

said respective TL message port defining the single path.

2. The method as recited in claim 1 includes providing a respective switch and link layer coupled to said transport layer;

said respective switch and link layer identifying a control TL messages having a same source TL, a same destination TL, and a same path, and transferring the identified control TL messages in an ordered control stream.

3. The method as recited in claim 1 wherein providing said respective TL message port identifying a port used to send and receive the control TL message for said source TL and said destination TL includes using a predefined protocol message sequence to identify a new TL message port.

4. The method as recited in claim 3 wherein using a predefined protocol message sequence to identify a new TL message port includes identifying one of the source TL or the destination TL having a lowest ID as a master TL and the other as a slave TL for the predefined protocol message sequence.

5. The method as recited in claim 4 wherein using a predefined protocol message sequence to identify a new TL message port includes the master TL selecting a pending TL message port and sending control messages to the slave TL using the pending TL message port.

6. The method as recited in claim 5 wherein using a predefined protocol message sequence to identify a new TL message port includes the slave TL sending control acknowledgement messages to the master TL using the pending TL message port.

7. The method as recited in claim 6 wherein using a predefined protocol message sequence to identify a new TL message port includes completing the predefined protocol message sequence, setting the pending TL message port to the TL message port for the pair of source TL and destination TL.

8. A circuit for implementing control using a single path in a multiple path interconnect system comprising:

a source interconnect chip coupled to a source device;

said source interconnect chip including a source transport layer (TL);

a destination interconnect chip coupled to the destination device;

said destination interconnect chip including a destination transport layer (TL);

each of said source TL and said destination TL including a respective TL message port used to send and receive a control TL message between a respective pair of said source TL and said destination TL;

said respective TL message port defining the single path for control messages.

9. The circuit as recited in claim 8 wherein said source interconnect chip and said destination interconnect chip includes a respective switch and link layer coupled to said respective source TL and said destination TL;

said respective switch and link layer identifying control TL messages having a same source TL, a same destination TL, and a same path, and transferring the identified control TL messages in an ordered control message stream.

10. The circuit as recited in claim 8 wherein said source TL and said destination TL use a predefined protocol message sequence to identify a new TL message port.

11. The circuit as recited in claim 10 wherein said predefined protocol message sequence includes said source TL and said destination TL identifying a master TL and a slave TL, said master TL selecting a pending TL message port and sending control messages to said slave TL using the pending TL message port.

12. The circuit as recited in claim 11 wherein said predefined protocol message sequence includes said slave TL sending control acknowledgement messages to said master TL using the pending TL message port.

13. The circuit as recited in claim 10 wherein said predefined protocol message sequence includes said source TL and said destination TL setting the new TL message port to said TL message port for the pair of said source TL and said destination TL, responsive to completing the predefined protocol message sequence.

14. A multiple-path local rack interconnect system comprising:

a plurality of interconnect chips including a source interconnect chip coupled to a source device and a destination interconnect chip coupled to the destination device;

a plurality of serial links connected between each of said plurality of interconnect chips;

said source interconnect chip including a source transport layer (TL);

said destination interconnect chip including a destination transport layer (TL);

each of said source TL and said destination TL including a respective TL message port used to send and receive a control TL message between a respective pair of said source TL and said destination TL;

said respective TL message port defining a single path for control messages.

15. The multiple-path local rack interconnect system as recited in claim 14 wherein said source interconnect chip and said destination interconnect chip includes a respective switch and link layer coupled to said respective source TL and said destination TL;

said respective switch and link layer identifying control TL messages having a same source TL, a same destination TL, and a same path, and transferring the identified control TL messages in an ordered control message stream.

16. The multiple-path local rack interconnect system as recited in claim 14 wherein said source TL and said destination TL use a predefined protocol message sequence to identify a new TL message port.

17. A design structure embodied in a machine readable medium used in a design process, the design structure comprising:

a circuit tangibly embodied in the machine readable medium used in the design process, said circuit for implementing control using a single path in a multiple path interconnect system, said circuit comprising;

a source interconnect chip coupled to a source device;

said source interconnect chip including a source transport layer (TL);

a destination interconnect chip coupled to the destination device;

said destination interconnect chip including a destination transport layer (TL);

each of said source TL and said destination TL including a respective TL message port used to send and receive a control TL message between a respective pair of said source TL and said destination TL;

said respective TL message port defining the single path for control messages, wherein the design structure, when read and used in the manufacture of a semiconductor chip produces a chip comprising said circuit.

18. The design structure of claim 17, wherein the design structure comprises a netlist, which describes said circuit.

19. The design structure of claim 17, wherein the design structure resides on storage medium as a data format used for the exchange of layout data of integrated circuits.

20. The design structure of claim 17, wherein the design structure includes at least one of test data files, characterization data, verification data, or design specifications.