MULTI-PROCESSOR SYSTEM AND LOCK ARBITRATION METHOD THEREOF

• US 20110246694A1
• Filed: 06/10/2011
• Published: 10/06/2011
• Est. Priority Date: 12/12/2008
• Status: Abandoned Application

• Current Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Original Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Inventors: Ichinose, Naoya
• Application Number:
  US13/157,958
• Publication Number:
  US 20110246694A1
• Time in Patent Office: Days
• US Class Current: 710/200
• CPC Class Codes: G06F 9/526 Mutual exclusion algorithms

Abstract

A multi-processor system of the present invention comprises a plurality of processors each configured to lock a shared resource and process a task; each of the processors including a lock wait information storage unit for storing lock wait information indicating whether or not the processor is waiting for acquirement of a lock of the shared resource; and a lock acquirement priority information storage unit for storing lock acquirement priority information indicating a priority according to which the shared resource is acquired; and each of the processors being configured to acquire the lock of the shared resource based on the lock wait information and the lock acquirement priority information.

Claims

1. A multi-processor system comprising:

a plurality of processors each configured to lock a shared resource and process a task;

each of the processors including a lock wait information storage unit for storing lock wait information indicating whether or not the processor is waiting for acquirement of a lock of the shared resource; and

a lock acquirement priority information storage unit for storing lock acquirement priority information indicating a priority according to which the shared resource is acquired; and

each of the processors being configured to acquire the lock of the shared resource based on the lock wait information and the lock acquirement priority information.

2. The multi-processor system according to claim 1, wherein the lock acquirement priority information storage unit comprises a register for storing the lock acquirement priority information.

3. The multi-processor system according to claim 1 being configured not to change the lock acquirement priority information.

4. The multi-processor system according to claim 1, being configured to change the lock acquirement priority information.

5. The multi-processor system according to claim 4, being configured to change the lock acquirement priority information in a specific cycle.

6. The multi-processor system according to claim 4, wherein each of the processors is configured to change the lock acquirement priority information, according to a priority of a task being executed or interrupt processing.

7. The multi-processor system according to claim 4, wherein each of the processors is configured to change the lock acquirement priority information, according to the number of times trial is made to acquire the lock.

8. The multi-processor system according to claim 1, wherein the lock wait information storage unit comprises a register for storing the lock wait information.

17. A camera comprising:

a controller unit including the multi-processor system as recited in claim 1, and the shared resource locked by each of the processors constituting the multi-processor system;

the controller unit being configured to control an operation of the camera.

9. A method of arbitrating a lock in a multi-processor system including a plurality of processors each configured to lock a shared resource and process a task;

the method comprising;

storing lock wait information indicating whether or not each of the processors is waiting for acquirement of a lock of the shared resource, in each of the processors;

storing lock acquirement priority information indicating a priority according to which each of the processors acquires a lock of the shared resource, in each of the processors; and

acquiring the lock of the shared resource based on the lock wait information and the lock acquirement priority information, in each of the processors.

10. The method of arbitrating the lock in the multi-processor system according to claim 9, wherein each of the processors stores the lock acquirement priority information in a register.

11. The method of arbitrating the lock in the multi-processor system according to claim 9, wherein each of the processors does not change the lock acquirement priority information.

12. The method of arbitrating the lock in the multi-processor system according to claim 9, wherein each of the processors changes the lock acquirement priority information.

13. The method of arbitrating the lock in the multi-processor system according to claim 12, wherein each of the processors changes the lock acquirement priority information in a specific cycle.

14. The method of arbitrating the lock in the multi-processor system according to claim 12, wherein each of the processors changes the lock acquirement priority information, according to a priority of a task being executed or interrupt processing.

15. The method of arbitrating the lock in the multi-processor system according to claim 12, wherein each of the processors changes the lock acquirement priority information, according to the number of times trial is made to acquire the lock.

16. The method of arbitrating the lock in the multi-processor system according to claim 9, wherein each of the processors stores the lock wait information in a register.