INTEGRATED CIRCUIT PROTECTED AGAINST HORIZONTAL SIDE CHANNEL ANALYSIS
First Claim
1. An integrated circuit comprising a multiplication function configured to execute a multiplication of at least two binary words x and y in a plurality of basic multiplication steps of components xi of word x by components yj of word y, i and j being iteration variables,wherein the multiplication function is further configured to execute two successive multiplications of binary words x and y by modifying, in a random or pseudo-random manner, an order in which the basic multiplication steps of components xi by components yj are executed.
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Accused Products
Abstract
An integrated circuit including a multiplication function configured to execute a multiplication operation of two binary words x and y including a plurality of basic multiplication steps of components xi of word x by components yj of word y is described. The multiplication function of the integrated circuit is configured to execute two successive multiplications by modifying, in a random or pseudo-random manner, an order in which the basic multiplication steps of components xi by components yj are executed.
27 Citations
17 Claims
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1. An integrated circuit comprising a multiplication function configured to execute a multiplication of at least two binary words x and y in a plurality of basic multiplication steps of components xi of word x by components yj of word y, i and j being iteration variables,
wherein the multiplication function is further configured to execute two successive multiplications of binary words x and y by modifying, in a random or pseudo-random manner, an order in which the basic multiplication steps of components xi by components yj are executed.
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12. A process for protecting against a side channel analysis of an integrated circuit configured to execute a multiplication operation of at least two binary words x and y and a plurality of basic multiplication steps of components xi of word x by components yj of word y, i and j being iteration variables, the process comprising:
modifying, in a random or pseudo-random manner, the order in which the integrated circuit executes basic multiplication steps of components xi by components yj, from one multiplication operation of binary words to another. - View Dependent Claims (13, 14, 15, 16, 17)
Specification