Receiver, System, and Memory with Memory Protection During Power Supply Transitions

• US 20110246808A1
• Filed: 06/21/2011
• Published: 10/06/2011
• Est. Priority Date: 09/15/2005
• Status: Active Grant

• Current Assignee: Silicon Laboratories Incorporated
• Original Assignee: Silicon Laboratories Incorporated
• Inventors: Green, Brian D., Kerth, Donald A., Marques, Augusto M.
• Granted Patent: US 8,489,058 B2
• Time in Patent Office: Days
• US Class Current: 713/340
• CPC Class Codes: H04B 1/16 Circuits
• CPC Class Codes: H04W 52/028 switching on or off only a part of the equipment circuit blocks
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

A receiver includes a memory, processing circuitry, and a memory protection unit. The processing circuitry is coupled to the memory, and has an input for receiving a radio frequency (RF) signal, and an output for providing an output signal at another frequency. The processing circuitry includes one or more independently powered components adapted to write data to the memory. The memory protection unit is coupled to the memory, and monitors a power supply voltage level corresponding to each independently powered component and, if the power supply voltage level changes during a power supply transition of an independently powered component in which the power supply voltage remains sufficiently large to power the independently powered component, to prevent write operations received from a corresponding one of the one or more independently powered components from occurring at least while the power supply voltage level is changing.

Claims

1. A receiver comprising:

a memory;

processing circuitry coupled to the memory, the processing circuitry having an input for receiving a radio frequency (RF) signal, and an output for providing an output signal at another frequency, the processing circuitry comprising one or more independently powered components adapted to write data to the memory; and

a memory protection unit coupled to the memory, the memory protection unit adapted to monitor a power supply voltage level corresponding to each of the one or more independently powered components and, if the power supply voltage level changes during a power supply transition of an independently powered component in which the power supply voltage remains sufficiently large to power the independently powered component, to prevent write operations received from a corresponding one of the one or more independently powered components from occurring at least while the power supply voltage level is changing.

2. The receiver of claim 1 further comprising:

a plurality of voltage regulators, each voltage regulator adapted to be shut down independently, each voltage regulator of the plurality of voltage regulators coupled to a respective one of the one or more independently powered components.

3. The receiver of claim 1 wherein the memory protection unit is adapted to lock the memory to prevent write operations prior to any changes to the power supply voltage level.

4. The receiver of claim 1 wherein the memory derives power from a first supply voltage at a first electrical potential during a first mode of operation and from a second supply voltage at a second electrical potential that is less than the first electrical potential during a second mode of operation, wherein the first supply voltage is collapsed during the second mode of operation.

5. The receiver of claim 4 wherein the memory protection unit is adapted to prevent any write operation to the memory during the second mode of operation.

6. The receiver of claim 1 wherein the memory protection unit is adapted to prevent any write operation to the memory if the power supply voltage level falls below a predetermined threshold level.

7. A system comprising:

a memory;

a first independently powered component operating in response to a first power supply voltage and capable of writing data to the memory; and

a first memory protection unit coupled to the memory, for monitoring the first power supply voltage and for preventing write operations from the first independently powered component to the memory from occurring in response to a power supply transition in which the first power supply voltage remains sufficiently large to power the first independently powered component, at least while the first power supply voltage is changing.

8. The system of claim 7 wherein the first memory protection unit is further adapted to prevent any write operation to the memory if the first power supply voltage falls below a predetermined threshold level.

9. The system of claim 7 further comprising:

a second independently powered component operating in response to a second power supply voltage and capable of writing data to the memory; and

a second memory protection unit coupled to the memory, for monitoring the second power supply voltage and for preventing write operations from the second independently powered component to the memory from occurring in response to a power supply transition in which the second power supply voltage remains sufficiently large to power the second independently powered component, at least while the second power supply voltage is changing.

10. The system of claim 9 wherein the second memory protection unit is further adapted to prevent any write operation to the memory if the second power supply voltage falls below a predetermined threshold level.

11. The system of claim 9 wherein:

the memory is characterized as being dual-ported and has a first port coupled to the first independently powered component through the first memory protection unit, and a second port coupled to the second independently powered component through the second memory protection unit.

12. The system of claim 7 wherein:

the first independently powered component is characterized as being a digital signal processor (DSP).

13. The system of claim 7 wherein the memory comprises:

a power switch having a first input for receiving a second power supply voltage, a second input for receiving a third power supply voltage less than the second power supply voltage, and a control input for receiving a power down signal, wherein the power switch powers the memory from the second power supply voltage in response to a first state of the power down signal, and from the third power supply voltage in response to a second state of the power down signal.

14. A method comprising:

powering a processing circuit using a first power supply voltage;

monitoring the first power supply voltage;

allowing write operations from the processing circuit to a memory over a first port when the first power supply voltage is not making a transition; and

preventing write operations from the processing circuit to the memory over the first port from occurring in response to a power supply transition of the first power supply voltage in which the first power supply voltage remains sufficiently large to power the processing circuit, at least while the first power supply voltage is changing.

15. The method of claim 14 further comprising:

preventing any write operation from occurring between the processing circuit and the memory over the first port in response to the first power supply voltage falling below a threshold.

16. The method of claim 14 further comprising:

powering a digital signal processor (DSP) using the first power supply voltage.

17. The method of claim 14 further comprising:

powering a logic circuit using a second power supply voltage;

monitoring the second power supply voltage;

allowing write operations from the logic circuit to the memory over a second port when the second power supply voltage is not making a transition; and

preventing write operations from the logic circuit to the memory over the second port from occurring in response to a power supply transition of the second power supply voltage in which the second power supply voltage remains sufficiently large to power the logic circuit, at least while the second power supply voltage is changing.

18. The method of claim 17 further comprising:

preventing any write operation from occurring between the logic circuit and the memory over the second port in response to the second power supply voltage falling below a threshold.

19. The method of claim 17 further comprising:

powering a portion of a receiver circuit using the second power supply voltage.

20. The method of claim 14 further comprising:

calibrating a receiver circuit to provide error correction factors; and

storing the error correction factors in the memory.