Testing Device and Testing Method

• US 20110246827A1
• Filed: 09/24/2010
• Published: 10/06/2011
• Est. Priority Date: 03/31/2010
• Status: Abandoned Application

• Current Assignee: Wistron Corporation
• Original Assignee: Wistron Corporation
• Inventors: Lin, Ching-An
• Application Number:
  US12/889,411
• Publication Number:
  US 20110246827A1
• Time in Patent Office: Days
• US Class Current: 714/27
• CPC Class Codes: G06F 11/22 Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing

Abstract

A testing device for testing an embedded system includes an interface capable of being coupled to the embedded system by means of insertion, a storage unit for storing data, and a processor for receiving a testing message corresponding to a testing command from the embedded system via the interface according to an enabling signal and storing the testing message into the storage unit when the interface is coupled to the embedded system.

Claims

1. A testing device for testing an embedded system, comprising:

an interface, capable of being coupled to the embedded system by means of insertion;

a storage unit, for storing data; and

a processor, for obtaining a testing message corresponding to a testing command from the embedded system via the interface according to an enabling signal and storing the testing message into the storage unit when the interface is coupled to the embedded system.

2. The testing device of claim 1, wherein the interface conforms to a standard of a universal serial bus.

3. The testing device of claim 1, further comprising a switch for generating the enabling signal.

4. The testing device of claim 1, wherein the processor is further utilized for establishing a communication connection with the embedded system via the interface according to the enabling signal when the interface is coupled to the embedded system.

5. The testing device of claim 1, wherein the processor is further utilized for deleting a message stored in the storage unit when a storing space of the storage unit is insufficient, so as to store the testing message into the storage unit.

6. The testing device of claim 1, further comprising a command storage unit for storing the testing command, wherein the processor is further utilized for outputting the testing command to the embedded system via the interface according to the enabling signal.

7. The testing device of claim 1, further comprising a memory for temporarily storing the testing command.

8. The testing device of claim 1, wherein the processor is further utilized for outputting the data stored in the storage unit to the embedded system via the interface according to the enabling signal when the interface is coupled to the embedded system.

9. The testing device of claim 1, wherein the embedded system is a computer system.

10. A testing method for testing an embedded system, comprising:

when a testing device is coupled to the embedded system, transmitting a testing message corresponding to a testing command from the embedded system to the testing device according to an enabling signal, to store the testing message into the testing device.

11. The testing method of claim 10, wherein when the testing device is coupled to the embedded system, the method further comprises establishing a communication connection between the testing device and the embedded system according to the enabling signal.

12. The testing method of claim 10, wherein when a storing space of the testing device is insufficient, the method further comprises deleting a message stored in the testing device, so as to store the testing message into the testing device.

13. The testing method of claim 10, further comprising the testing device storing the testing command and outputting the testing command to the embedded system.

14. The testing method of claim 10, further comprising outputting data stored by the testing device to the embedded system according to the enabling signal when the testing device is coupled to the embedded system.

15. The testing method of claim 10, wherein the embedded system is a computer system.