DEVICE FOR USE IN INSPECTING A CPU AND METHOD THEREOF

• US 20110246838A1
• Filed: 12/15/2010
• Published: 10/06/2011
• Est. Priority Date: 03/31/2010
• Status: Active Grant

• Current Assignee: RDC Semiconductor Co. Ltd.
• Original Assignee: RDC Semiconductor Co. Ltd.
• Inventors: Huang, Chun-Jieh, Yap, Chang Cheng, Lin, Huan-Chau
• Granted Patent: US 8,489,927 B2
• Time in Patent Office: Days
• US Class Current: 714/48
• CPC Class Codes: G06F 11/2236 to test CPU or processors

Abstract

A device for use in inspecting a CPU and a method thereof are provided. The device comprises a receiving interface and a processor. The receiving interface receives a first data stream from the CPU when the CPU executes a reference hardware inspection program in a first time interval, and receives a second data stream from the CPU when the CPU executes the reference hardware inspection program in a second time interval. The processor sets the first data stream as a good log, and sets the second data stream as an erroneous log. The processor compares the good log and the erroneous log to determine a segment of the erroneous log as an erroneous range, and determine a defect of the CPU according to the erroneous range.

Claims

1. A method for inspecting a central processing unit (CPU), the method being adapted for use in an inspection device, the inspection device being electrically connected to the CPU and comprising a receiving interface and a processor, the method comprising the following steps of:

(a) enabling the receiving interface to receive a first data stream from the CPU when the CPU executes a reference hardware inspection program in a first time interval;

(b) enabling the processor to set the first data stream as a good log;

(c) enabling the receiving interface to receive a second data stream from the CPU when the CPU executes the reference hardware inspection program in a second time interval;

(d) enabling the processor to set the second data stream as an erroneous log;

(e) enabling the processor to compare the good log with the erroneous log to determine a segment of the erroneous log as an erroneous range; and

(f) enabling the processor to determine a defect of the CPU according to the erroneous range.

2. The method as claimed in claim 1, wherein the CPU comprises a CPU core, a cache, a memory management unit (MMU) and a code interface, the CPU is electrically connected to a dynamic random access memory (DRAM) and a hard disk, the reference hardware inspection program is stored in the hard disk, the CPU core is configured to load the reference hardware inspection program into the cache and the DRAM to execute the reference hardware inspection program, the MMU is configured to record an address mapping relationship of the reference hardware inspection program among the cache, the DRAM and the hard disk, the erroneous range is a linear address range, the first data stream comprises a first code data stream, the second data stream comprises a second code data stream, the step (a) is to enable the receiving interface to receive the first code data stream from the code interface, and the step (c) is to enable the receiving interface to receive the second code data stream from the code interface.

3. The method as claimed in claim 2, wherein the step (b) comprises the following steps of:

(b1) enabling the processor to store the first code data stream into a storage device;

(b2) enabling the processor to, after the CPU core has executed the reference hardware inspection program in the first time interval, determine that an error message is not generated as a result of the execution of the reference hardware inspection program by the CPU; and

(b3) enabling the processor to set the first code data stream as the good log according to the result of the step (b2); and

the step (d) comprises the following steps of;

(d1) enabling the processor to store the second code data stream into the storage device;

(d2) enabling the processor to, when the CPU core is executing the reference hardware inspection program in the second time interval, determine that the error message is generated as a result of the execution of the reference hardware inspection program by the CPU; and

(d3) enabling the processor to set the second code data stream as the erroneous log according to the result of the step (d2).

4. The method as claimed in claim 3, wherein the step (e) comprises the following steps of:

(e1) enabling the processor to read the good log and the erroneous log from the storage device; and

(e2) enabling the processor to compare the second code data stream with the first code data stream to determine the segment where the second code data stream is different from the first code data stream as the erroneous range.

5. The method as claimed in claim 4, wherein the inspection device further comprises a dump memory and a transmitting interface, the dump memory is electrically connected to the processor and the receiving interface, the CPU further comprises a program counter interface, a store interface, a load interface and a Joint Test Action Group (JTAG) interface, the JTAG interface is connected to a workstation, and the step (f) comprises the following steps of:

(f1) enabling the processor to determine a candidate code range of the reference hardware inspection program according to the erroneous range, wherein the candidate code range defines a plurality of codes for accessing a plurality of linear addresses of the hard disk;

(f2) enabling the receiving interface to, when the CPU core executes the reference hardware inspection program in a third time interval, receive a plurality of data stored in the plurality of linear addresses of the hard disk;

(f3) enabling the receiving interface to store the plurality of data received into the dump memory;

(f4) enabling the processor to, when the CPU core executes one of the plurality of codes again to access a candidate linear address, retrieve a first predetermined portion of the data corresponding to the candidate linear address from the cache as a first data, wherein the candidate linear address is one of the plurality of linear addresses;

(f5) enabling the processor to, after the step (f4), retrieve a second predetermined portion of the data corresponding to the candidate linear address from the dump memory as a second data;

(f6) enabling the processor to determine that the first data and the second data are different from each other;

(f7) enabling the processor to determine that the code for accessing the candidate linear address is related to the defect of the CPU according to the result of the step (f6);

(f8) enabling the receiving interface to, when the execution of the reference hardware inspection program by the CPU core in a fourth time interval reaches the candidate code range, receive an interval code data stream, an interval counter data stream, an interval store data stream and an interval load data stream from the code interface, the counter interface, the store interface and the load interface respectively, wherein when the execution of the reference hardware inspection program by the CPU core in the fourth time interval reaches the candidate code range, the workstation receives a working status of the CPU core through the JTAG interface;

(f9) enabling the processor to, after the step (f8), convert the interval code data stream, the interval counter data stream, the interval store data stream and the interval load data stream into a problem interval log which is readable by a workstation; and

(f10) enabling the processor to transmit the problem interval log to the workstation through the transmitting interface, so as to determine the defect of the CPU by means of the workstation according to the problem interval log and the working status.

6. The method as claimed in claim 5, wherein the first predetermined portion is a plurality of bits of the data corresponding to the candidate linear address stored in the cache, the second predetermined portion is a plurality of bits of the data corresponding to the candidate linear address stored in the dump memory, and amounts and positions of the bits of the first predetermined portion and the second predetermined portion are the same.

7. The method as claimed in claim 5, wherein the first predetermined portion is a whole of the data corresponding to the candidate linear address stored in the cache, and the second predetermined portion is a whole of the data corresponding to the candidate linear address stored in the dump memory.

8. The method as claimed in claim 5, wherein the CPU core has a plurality of registers, and the working status of the CPU refers to a status of the CPU core and a status of each of the plurality of registers.

9. The method as claimed in claim 5, wherein the workstation is an environment for implementing an electronic design automation (EDA) tool, and the CPU is an environment of a field-programmable gate array (FPGA).

10. The method as claimed in claim 1, wherein the CPU comprises a CPU core, a program counter interface, the first data stream comprises a first counter data stream, the second data stream comprises a second counter data stream, the step (a) is to enable the receiving interface to receive the first counter data stream from the program counter interface, and the step (c) is to enable the receiving interface to receive the second counter data stream from the program counter interface.

11. The method as claimed in claim 10, wherein the step (b) comprises the following steps of:

(b1) enabling the processor to store the first counter data stream into a storage device;

(b2) enabling the processor to, after the CPU has executed the reference hardware inspection program in the first time interval, determine that an error message is not generated as a result of the execution of the reference hardware inspection program by the CPU; and

(b3) enabling the processor to set the first counter data stream as the good log according to the result of the step (b2); and

the step (d) comprises the following steps of;

(d1) enabling the processor to store the second counter data stream into the storage device;

(d2) enabling the processor to, when the CPU is executing the reference hardware inspection program in the second time interval, determine that an error message is generated as a result of the execution of the reference hardware inspection program by the CPU; and

(d3) enabling the processor to set the second counter data stream as the erroneous log according to the result of the step (d2).

12. The method as claimed in claim 11, wherein the step (e) comprises the following steps of:

(e1) enabling the processor to read the good log and the erroneous log from the storage device; and

(e2) enabling the processor to compare the second counter data stream with the first counter data stream to determine the segment where the second counter data stream is different from the first counter data stream as the erroneous range.

13. The method as claimed in claim 12, wherein the inspection device further comprises a transmitting interface, the CPU further comprises a code interface, a store interface, a load interface and a JTAG interface, the JTAG interface is connected to a workstation, and the step (f) comprises the following steps of:

(f1) enabling the processor to determine a candidate code range of the reference hardware inspection program according to the erroneous range;

(f2) enabling the receiving interface to, when the execution of the reference hardware inspection program by the CPU core in a third time interval reaches the candidate code range, receive an interval counter data stream, an interval code data stream, an interval store data stream and an interval load data stream from the counter interface, the code interface, the store interface and the load interface respectively, wherein the workstation receives a working status of the CPU core through the JTAG interface in the third time interval;

(f3) enabling the processor to convert the interval counter data stream, the interval code data stream, the interval store data stream and the interval load data stream into a problem interval log which is readable by a workstation; and

(f4) enabling the processor to transmit the problem interval log to the workstation through the transmitting interface so as to determine the defect of the CPU by means of the workstation according to the problem interval log and the working status.

14. The method as claimed in claim 13, wherein the CPU core has a plurality of registers, and the working status of the CPU refers to a status of the CPU core and a status of each of the registers.

15. The method as claimed in claim 13, wherein the workstation is an environment for implementing an EDA tool, and the CPU is an environment of an FPGA.

16. A device for use in inspecting a CPU, the device being electrically connected to the CPU and comprising:

a receiving interface, being configured to receive a first data stream from the CPU when the CPU executes a reference hardware inspection program in a first time interval and receive a second data stream from the CPU when the CPU executes the reference hardware inspection program in a second time interval; and

a processor, being configured to set the first data stream as a good log, set the second data stream as an erroneous log, compare the good log with the erroneous log to determine a segment of the erroneous log as an erroneous range and determine a defect of the CPU according to the erroneous range.

17. The device as claimed in claim 16, wherein the CPU comprises a CPU core, a cache, an MMU and a code interface, the CPU is electrically connected to a DRAM and a hard disk, the reference hardware inspection program is stored in the hard disk, the CPU core is configured to load the reference hardware inspection program into the cache and the DRAM to execute the reference hardware inspection program, the MMU is configured to record an address mapping relationship of the reference hardware inspection program among the cache, the DRAM and the hard disk, the erroneous range is a linear address range, the first data stream comprises a first code data stream, the second data stream comprises a second code data stream, and the receiving interface is configured to receive the first code data stream and the second code data stream from the code interface of the CPU.

18. The device as claimed in claim 17, wherein the processor is further configured to:

store the first code data stream into a storage device,

after the CPU core has executed the reference hardware inspection program in the first time interval, determine that an error message is not generated as a result of the execution of the reference hardware inspection program by the CPU,

set the first code data stream as the good log according to the determination result that a error message is not generated as a result of the execution of the reference hardware inspection program in the first time interval,

store the second code data stream into the storage device,

when the CPU is executing the reference hardware inspection program in the second time interval, determine that the error message is generated as a result of the execution of the reference hardware inspection program by the CPU, and

set the second code data stream as the erroneous log according to the determination result that the error message is generated as a result of the execution of the reference hardware inspection program in the second time interval.

19. The device as claimed in claim 18, wherein the processor is further configured to read the good log and the erroneous log from the storage device, and compare the second code data stream with the first code data stream to determine the segment where the second code data stream is different from the first code data stream as the erroneous range.

20. The device as claimed in claim 19, wherein the device further comprises a dump memory and a transmitting interface, the dump memory is electrically connected to the processor and the receiving interface, the CPU further comprises a program counter interface, a store interface, a load interface and a JTAG interface, the JTAG interface is connected to a workstation, and the device is further configured to execute the following operations:

the processor is further configured to determine a candidate code range of the reference hardware inspection program according to the erroneous range, wherein the candidate code range defines a plurality of codes for accessing a plurality of linear addresses of the hard disk,

the receiving interface is further configured to, when the CPU core executes the reference hardware inspection program in a third time interval, receive a plurality of data stored in the plurality of linear addresses of the hard disk, the receiving interface is further configured to store the plurality of data received into the dump memory,

the processor is further configured to, when the CPU core executes one of the plurality of codes again to access a candidate linear address, retrieve a first predetermined portion of the data corresponding to the candidate linear address from the cache as a first data, wherein the candidate linear address is one of the plurality of linear addresses,

the processor is further configured to retrieve a second predetermined portion of the data corresponding to the candidate linear address from the dump memory as a second data, the processor is further configured to determine that the first data and the second data are different from each other, and determine that the code for accessing the candidate linear address is related to the defect of the CPU according to the determination result that the first data and the second data are different from each other, the receiving interface is further configured to, when the execution of the reference hardware inspection program by the CPU core in a fourth time interval reaches the candidate code range, receive an interval code data stream, an interval counter data stream, an interval store data stream and an interval load data stream from the code interface, the counter interface, the store interface and the load interface respectively, wherein the workstation receives a working status of the CPU core through the JTAG interface in the fourth time interval,

the processor is further configured to convert the interval code data stream, the interval counter data stream, the interval store data stream and the interval load data stream into a problem interval log which is readable by a workstation, and

the processor is further configured to transmit the problem interval log to the workstation through the transmitting interface so as to determine the defect of the CPU by means of the workstation according to the problem interval log and the working status.

21. The device as claimed in claim 20, wherein the CPU core has a plurality of registers, and the working status of the CPU refers to a status of the CPU core and a status of each of the plurality of registers.

22. The device as claimed in claim 20, wherein the workstation is an environment for implementing an EDA tool, and the CPU is an environment of an FPGA.

23. The device as claimed in claim 20, wherein the first predetermined portion is a plurality of bits of the data corresponding to the candidate linear address stored in the cache, the second predetermined portion is a plurality of bits of the data corresponding to the candidate linear address stored in the dump memory, and amounts and positions of the bits of the first predetermined portion and the second predetermined portion are the same.

24. The device as claimed in claim 20, wherein the first predetermined portion is a whole of the data corresponding to the candidate linear address stored in the cache, and the second predetermined portion is a whole of the data corresponding to the candidate linear address stored in the dump memory.

25. The device as claimed in claim 16, wherein the CPU comprises a CPU core, a program counter interface, the first data stream comprises a first counter data stream, the second data stream comprises a second counter data stream, and the receiving interface is configured to receive the first counter data stream and the second counter data stream from the program counter interface.

26. The device as claimed in claim 25, wherein the processor is further configured to:

store the first counter data stream into a storage device,

after the CPU core has executed the reference hardware inspection program in the first time interval, determine that an error message is not generated as a result of the execution of the reference hardware inspection program by the CPU,

set the first counter data stream as the good log according to the determination result that the error message is not generated as a result of the execution of the reference hardware inspection program in the first time interval,

store the second counter data stream into the storage device,

when the CPU core is executing the reference hardware inspection program in the second time interval, determine that the error message is generated as a result of the execution of the reference hardware inspection program by the CPU, and

set the second counter data stream as the erroneous log according to the determination result that the error message is generated as a result of the execution of the reference hardware inspection program in the second time interval.

27. The device as claimed in claim 26, wherein the processor is further configured to read the good log and the erroneous log from the storage device, and compare the second counter data stream with the first counter data stream to determine the segment where the second counter data stream is different from the first counter data stream as the erroneous range.

28. The device as claimed in claim 27, wherein the device further comprises a transmitting interface, the CPU further comprises a code interface, a store interface, a load interface and a JTAG interface, the JTAG interface is connected to a workstation, the processor is further configured to determine a candidate code range of the reference hardware inspection program according to the erroneous range, the receiving interface is further configured to, when the execution of the reference hardware inspection program by the CPU core in a third time interval reaches the candidate code range, receive an interval counter data stream, an interval code data stream, an interval store data stream and an interval load data stream from the counter interface, the code interface, the store interface and the load interface respectively, the workstation receives a working status of the CPU core through the JTAG interface in the third time interval, the processor is further configured to convert the interval counter data stream, the interval code data stream, the interval store data stream and the interval load data stream into a problem interval log which is readable by a workstation, and transmit the problem interval log to the workstation through the transmitting interface so as to determine the defect of the CPU by means of the workstation according to the problem interval log and the working status.

29. The device as claimed in claim 28, wherein the CPU core has a plurality of registers, and the working status of the CPU refers to a status of the CPU core and a status of each of the registers.

30. The device as claimed in claim 28, wherein the workstation is an environment for implementing an EDA tool, and the CPU is an environment of an FPGA.