TRANSISTOR

• US 20110248266A1
• Filed: 03/31/2011
• Published: 10/13/2011
• Est. Priority Date: 04/07/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Kayama, Masayo, Miyake, Hiroyuki
• Granted Patent: US 9,401,407 B2
• Time in Patent Office: Days
• US Class Current: 257/57
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

An object is to provide a transistor having a novel electrode structure capable of substantially maintaining on-state current while parasitic capacitance generated in an overlap portion between a source electrode layer (a drain electrode layer) and a gate electrode layer is reduced. Parasitic capacitance is reduced by using a source electrode layer and a drain electrode in a comb shape in a transistor. Curved current flowing from side edges of electrode tooth portions can be generated by controlling the width of an end of a comb-shaped electrode layer or the interval between the electrode tooth portions. This curved current compensates for a decrease in linear current due to a comb electrode shape; thus, on-state current can be kept unchanged even when parasitic capacitance is reduced.

Claims

1. A transistor comprising:

a source electrode layer in a comb shape, including electrode tooth portions arranged adjacently at a predetermined interval and a connection portion for connecting the electrode tooth portions; and

a drain electrode layer in a comb shape, including electrode tooth portions arranged adjacently at a predetermined interval and a connection portion for connecting the electrode tooth portions,

wherein the source electrode layer and the drain electrode layer are disposed such that the electrode tooth portions of the source electrode layer and the electrode tooth portions of the drain electrode layer face each other without interdigitating with each other.

2. The transistor according to claim 1, further comprising:

a gate electrode layer;

a gate insulating layer in contact with the gate electrode layer; and

a semiconductor layer overlapping with the gate electrode layer with the gate insulating layer interposed therebetween,

wherein an edge of the source electrode layer is in contact with the semiconductor layer and overlaps with the gate electrode layer with the gate insulating layer and the semiconductor layer interposed therebetween, and

wherein an edge of the drain electrode layer is in contact with the semiconductor layer and overlaps with the gate electrode layer with the gate insulating layer and the semiconductor layer interposed therebetween.

3. The transistor according to claim 2, wherein the semiconductor layer comprises an oxide semiconductor.

4. The transistor according to claim 1, wherein the connection portion of the source electrode layer and the gate electrode layer do not overlap with each other, and wherein the connection portion of the drain electrode layer and the gate electrode layer do not overlap with each other.

5. The transistor according to claim 1, wherein a sum of widths of ends of the electrode tooth portions of the source electrode layer is ⅜

to 1/1 of a width of the source electrode layer and ⅜

to 8/3 of a width of the drain electrode layer.

6. The transistor according to claim 1, wherein a sum of widths of ends of the electrode tooth portions of the drain electrode layer is ⅜

to 1/1 of a width of the drain electrode layer and ⅜

to 8/3 of a width of the source electrode layer.

7. The transistor according to claim 1, wherein an interval between adjacent electrode tooth portions of at least one of the source electrode layer and the drain electrode layer is greater than 0 μ

m and less than or equal to 5 μ

m.

8. The transistor according to claim 1, wherein an end of one of the electrode tooth portions of the source electrode layer and an end of one of the electrode tooth portions of the drain electrode layer face each other along a same length.

9. A transistor comprising:

a source electrode layer in a comb shape, including electrode tooth portions arranged adjacently at a predetermined interval and a connection portion for connecting the electrode tooth portions; and

a drain electrode layer in a comb shape, including electrode tooth portions arranged adjacently at a predetermined interval and a connection portion for connecting the electrode tooth portions,

wherein the source electrode layer and the drain electrode layer are disposed such that the electrode tooth portions of the source electrode layer and the electrode tooth portions of the drain electrode layer face each other without interdigitating with each other, and

wherein an end of one of the electrode tooth portions of the source electrode layer and an end of one of the electrode tooth portions of the drain electrode layer face each other along a length different from a length of the end of the electrode tooth portion of the source electrode layer or a length of the end of the electrode tooth portion of the drain electrode layer.

10. The transistor according to claim 9, further comprising:

a gate electrode layer;

a gate insulating layer in contact with the gate electrode layer; and

a semiconductor layer overlapping with the gate electrode layer with the gate insulating layer interposed therebetween,

wherein an edge of the source electrode layer is in contact with the semiconductor layer and overlaps with the gate electrode layer with the gate insulating layer and the semiconductor layer interposed therebetween, and

wherein an edge of the drain electrode layer is in contact with the semiconductor layer and overlaps with the gate electrode layer with the gate insulating layer and the semiconductor layer interposed therebetween.

11. The transistor according to claim 10, wherein the semiconductor layer comprises an oxide semiconductor.

12. The transistor according to claim 9, wherein the connection portion of the source electrode layer and the gate electrode layer do not overlap with each other, and wherein the connection portion of the drain electrode layer and the gate electrode layer do not overlap with each other.

13. The transistor according to claim 9, wherein a sum of widths of ends of the electrode tooth portions of the source electrode layer is ⅜

to 1/1 of a width of the source electrode layer and ⅜

to 8/3 of a width of the drain electrode layer.

14. The transistor according to claim 9, wherein a sum of widths of ends of the electrode tooth portions of the drain electrode layer is ⅜

to 1/1 of a width of the drain electrode layer and ⅜

to 8/3 of a width of the source electrode layer.

15. The transistor according to claim 9, wherein an interval between adjacent electrode tooth portions of at least one of the source electrode layer and the drain electrode layer is greater than 0 μ

m and less than or equal to 5 μ

m.

16. A transistor comprising:

a source electrode layer in a comb shape, including electrode tooth portions arranged adjacently at a predetermined interval and a connection portion for connecting the electrode tooth portions; and

a drain electrode layer,

wherein the source electrode layer and the drain electrode layer are disposed such that the electrode tooth portions of the source electrode layer and the drain electrode layer face each other.

17. The transistor according to claim 16, further comprising:

a gate electrode layer;

a gate insulating layer in contact with the gate electrode layer; and

a semiconductor layer overlapping with the gate electrode layer with the gate insulating layer interposed therebetween,

wherein an edge of the source electrode layer is in contact with the semiconductor layer and overlaps with the gate electrode layer with the gate insulating layer and the semiconductor layer interposed therebetween, and

wherein an edge of the drain electrode layer is in contact with the semiconductor layer and overlaps with the gate electrode layer with the gate insulating layer and the semiconductor layer interposed therebetween.

18. The transistor according to claim 17, wherein the semiconductor layer comprises an oxide semiconductor.

19. The transistor according to claim 16, wherein the connection portion of the source electrode layer and the gate electrode layer do not overlap with each other.

20. The transistor according to claim 16, wherein a sum of widths of ends of the electrode tooth portions of the source electrode layer is ⅜

to 1/1 of a width of the source electrode layer and ⅜

to 8/3 of a width of the drain electrode layer.

21. The transistor according to claim 16, wherein an interval between adjacent electrode tooth portions of the source electrode layer is greater than 0 μ

m and less than or equal to 5 μ

m.

22. The transistor according to claim 16,

wherein an entire edge of the drain electrode layer, which faces the source electrode layer, is straight.

23. A transistor comprising:

a drain electrode layer in a comb shape, including electrode tooth portions arranged adjacently at a predetermined interval and a connection portion for connecting the electrode tooth portions; and

a source electrode layer,

wherein the source electrode layer and the drain electrode layer are disposed such that the source electrode layer and the electrode tooth portions of the drain electrode layer face each other.

24. The transistor according to claim 23, further comprising:

a gate electrode layer;

a gate insulating layer in contact with the gate electrode layer; and

a semiconductor layer overlapping with the gate electrode layer with the gate insulating layer interposed therebetween,

wherein an edge of the source electrode layer is in contact with the semiconductor layer and overlaps with the gate electrode layer with the gate insulating layer and the semiconductor layer interposed therebetween, and

wherein an edge of the drain electrode layer is in contact with the semiconductor layer and overlaps with the gate electrode layer with the gate insulating layer and the semiconductor layer interposed therebetween.

25. The transistor according to claim 24, wherein the semiconductor layer comprises an oxide semiconductor.

26. The transistor according to claim 23, wherein the connection portion of the drain electrode layer and the gate electrode layer do not overlap with each other.

27. The transistor according to claim 23, wherein a sum of widths of ends of the electrode tooth portions of the drain electrode layer is ⅜

to 1/1 of a width of the drain electrode layer and ⅜

to 8/3 of a width of the source electrode layer.

28. The transistor according to claim 23, wherein an interval between adjacent electrode tooth portions of the drain electrode layer is greater than 0 μ

m and less than or equal to 5 μ

m.

29. The transistor according to claim 23,

wherein an entire edge of the source electrode layer, which faces the drain electrode layer, is straight.

30. A transistor comprising:

a gate electrode layer;

a gate insulating layer adjacent to the gate electrode layer;

a semiconductor layer adjacent to the gate electrode layer with the gate insulating layer interposed therebetween;

a source electrode layer in electrical contact with the semiconductor layer; and

a drain electrode layer in electrical contact with the semiconductor layer,

wherein at least one of the source electrode layer and the drain electrode layer has at least a first inner edge and a second inner edge, each of the first inner edge and the second inner edge facing the other of the source electrode layer and the drain electrode layer,

wherein the first inner edge is closer to the other of the source electrode layer and the drain electrode layer than the second inner edge, and

wherein the first inner edge overlaps with the gate electrode layer and the second inner edge does not overlap with the gate electrode.

31. The transistor according to claim 30, wherein the semiconductor layer comprises an oxide semiconductor.

32. The transistor according to claim 30, wherein a width of the first inner edge of the one of the source electrode layer and the drain electrode layer is ⅜

to 1/1 of a width of the one of the source electrode layer and the drain electrode layer and ⅜

to 8/3 of a width of the other of the source electrode layer and the drain electrode layer.

33. The transistor according to claim 30, wherein a width of the second inner edge is greater than 0 μ

m and less than or equal to 5 μ

m.