SEMICONDUCTOR DEVICE

• US 20110248286A1
• Filed: 04/07/2011
• Published: 10/13/2011
• Est. Priority Date: 04/08/2010
• Status: Active Grant

• Current Assignee: Hitachi Power Semiconductor Device, Ltd. (Hitachi, Ltd.)
• Original Assignee: Hitachi, Ltd.
• Inventors: ONOSE, Hidekatsu
• Granted Patent: US 8,816,355 B2
• Time in Patent Office: Days
• US Class Current: 257/77
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1004 Base region of bipolar transistors
• CPC Class Codes: H01L 29/1066 Gate region of field-effect devices with PN junction gate
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/6606 the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/7302 structurally associated with other devices assemblies of devices H01L25/00; integrated circuits H01L27/00; IGBT H01L29/7393
• CPC Class Codes: H01L 29/7803 structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/8083 Vertical transistors SIT H01L29/7722
• CPC Class Codes: H01L 29/861 Diodes

Abstract

For suggesting a structure capable of achieving both a low start-up voltage and high breakdown voltage, a SiC vertical diode includes a cathode electrode, an n⁺⁺ cathode layer, an n⁻ drift layer on the n⁺⁺ cathode layer, a pair of p⁺ regions, an n⁺ channel region formed between the n⁻ drift layer and the p⁺ region and sandwiched between the pair of p⁺ regions, n⁺⁺ anode regions and an anode electrode formed on the n⁺⁺ anode regions and the p⁺ regions.

Claims

1. A semiconductor device using silicon carbide as a substrate, the semiconductor device comprising:

a cathode electrode;

a cathode layer of a first conductivity type formed on the cathode electrode of the substrate and having a first impurity concentration;

a drift layer of the first conductivity type formed on the cathode layer and having a second impurity concentration lower than the first impurity concentration;

a pair of first semiconductor regions of a second conductivity type opposite to the first conductivity type formed above the drift layer;

a channel region of the first conductivity type formed between the drift layer and the first semiconductor region and sandwiched between the pair of first semiconductor regions and having a third impurity concentration lower than the first impurity concentration and higher than the second impurity concentration;

an anode region of the first conductivity type formed on the channel region and having a fourth impurity concentration higher than the third impurity concentration; and

an anode electrode formed on the pair of first semiconductor regions and the anode region.

2. The semiconductor device according to claim 1,

wherein the first conductivity type is an n type and the second conductivity type is a p type.

3. The semiconductor device according to claim 1,

wherein the second impurity concentration is 5×

10¹⁵ cm<sup>−

3</sup> or higher and 1.8×

10¹⁶ cm<sup>−

3</sup> or lower.

4. The semiconductor device according to claim 1,

wherein the second impurity concentration is 8×

10¹⁵ cm<sup>−

3</sup> or higher and 1.5×

10¹⁶ cm<sup>−

3</sup> or lower.

5. The semiconductor device according to claim 1,

wherein the third impurity concentration is 8×

10¹⁶ cm<sup>−

3</sup> or higher and 1.8×

10¹⁷ cm<sup>−

3</sup> or lower.

6. The semiconductor device according to claim 3,

wherein the third impurity concentration is 8×

10¹⁶ cm<sup>−

3</sup> or higher and 1.8×

10¹⁷ cm<sup>−

3</sup> or lower.

7. A semiconductor device using silicon carbide as a substrate, the semiconductor device comprising:

a first region of the substrate in which a diode is formed;

a second region of the substrate in which a junction FET is formed;

a first electrode formed in the first region and the second region;

a first semiconductor region of a first conductivity type formed on the first electrode and having a first impurity concentration;

a second semiconductor region of the first conductivity type formed on the first semiconductor region and having a second impurity concentration lower than the first impurity concentration;

a pair of third semiconductor regions of a second conductivity type opposite to the first conductivity type formed above the second semiconductor region in the first region;

a pair of fourth semiconductor regions of the second conductivity type formed above the second semiconductor region in the second region;

fifth semiconductor regions of the first conductivity type formed between the second and third semiconductor regions and between the second and fourth semiconductor regions, sandwiched between the pair of third semiconductor regions and between the pair of fourth semiconductor regions and having a third impurity concentration lower than the first impurity concentration and higher than the second impurity concentration;

sixth semiconductor regions of the first conductivity type formed on the fifth semiconductor regions in the first region and having a fourth impurity concentration higher than the third impurity concentration;

seventh semiconductor regions of the first conductivity type formed on the fifth semiconductor regions in the second region and having a fifth impurity concentration higher than the third impurity concentration;

a second electrode formed on the third and sixth semiconductor regions;

a third electrode formed on the seventh semiconductor regions; and

fourth electrodes formed on the fourth semiconductor regions.

8. The semiconductor device according to claim 7,

wherein the first conductivity type is an n type and the second conductivity type is a p type.

9. The semiconductor device according to claim 7,

wherein the first electrode functions as both a cathode electrode of the diode and a drain electrode of the junction FET,

the second electrode is an anode electrode of the diode,

the third electrode is a source electrode of the junction FET, and

the fourth electrode is a gate electrode of the junction FET.

10. The semiconductor device according to claim 7,

wherein a width between the pair of fourth semiconductor regions is smaller than a width between the pair of third semiconductor regions.

11. The semiconductor device according to claim 7,

wherein the second impurity concentration is 5×

10¹⁵ cm<sup>−

3</sup> or higher and 1.8×

10¹⁶ cm<sup>−

3</sup> or lower.

12. The semiconductor device according to claim 7,

wherein the third impurity concentration is 8×

10¹⁶ cm<sup>−

3</sup> or higher and 1.8×

10¹⁷ cm<sup>−

3</sup> or lower.

13. The semiconductor device according to claim 11,

wherein the third impurity concentration is 8×

10¹⁶ cm<sup>−

3</sup> or higher and 1.8×

10¹⁷ cm<sup>−

3</sup> or lower.

14. A semiconductor device using silicon carbide as a substrate, the semiconductor device comprising:

a first region of the substrate in which a diode is formed;

a second region of the substrate in which a MOSFET is formed;

a first electrode formed in the first region and the second region;

a first semiconductor region of a first conductivity type formed on the first electrode and having a first impurity concentration;

a second semiconductor region of the first conductivity type formed on the first semiconductor region and having a second impurity concentration lower than the first impurity concentration;

a pair of third semiconductor regions of a second conductivity type opposite to the first conductivity type formed above the second semiconductor region in the first region;

a fourth semiconductor region of the second conductivity type formed above the second semiconductor region in the second region;

a fifth semiconductor region of the first conductivity type formed between the second and third semiconductor regions and between the second and fourth semiconductor regions, sandwiched between the pair of third semiconductor regions and having a third impurity concentration lower than the first impurity concentration and higher than the second impurity concentration;

sixth semiconductor regions of the first conductivity type formed on the fifth semiconductor region in the first region and having a fourth impurity concentration higher than the third impurity concentration;

a seventh semiconductor region of the first conductivity type formed on the fifth semiconductor region in the second region and having a fifth impurity concentration higher than the third impurity concentration;

a second electrode formed on the third and sixth semiconductor regions;

a third electrode formed on the seventh semiconductor region; and

a gate electrode of the MOSFET disposed to the fourth semiconductor regions via an insulating film.

15. The semiconductor device according to claim 14,

wherein the first conductivity type is an n type and the second conductivity type is a p type.

16. The semiconductor device according to claim 14,

wherein the first electrode functions as both a cathode electrode of the diode and a drain electrode of the MOSFET,

the second electrode is an anode electrode of the diode, and

the third electrode is a source electrode of the MOSFET.

17. The semiconductor device according to claim 14,

wherein the second impurity concentration is 5×

10¹⁵ cm<sup>−

3</sup> or higher and 1.8×

10¹⁶ cm<sup>−

3</sup> or lower.

18. The semiconductor device according to claim 14,

wherein the third impurity concentration is 8×

10¹⁶ cm<sup>−

3</sup> or higher and 1.8×

10¹⁷ cm<sup>−

3</sup> or lower.

19. The semiconductor device according to claim 17,

wherein the third impurity concentration is 8×

10¹⁶ cm<sup>−

3</sup> or higher and 1.8×

10¹⁷ cm<sup>−

3</sup> or lower.