CHIP PACKAGE AND METHOD FOR FORMING THE SAME

• US 20110248310A1
• Filed: 04/06/2011
• Published: 10/13/2011
• Est. Priority Date: 04/07/2010
• Status: Active Grant

• Current Assignee: Xintec Incorporated
• Original Assignee: Xintec Incorporated
• Inventors: Liu, Chien-Hung, CHENG, Chia-Ming
• Granted Patent: US 8,362,515 B2
• Time in Patent Office: Days
• US Class Current: 257/99
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/02371 connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/02372 connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49805 the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01021 Scandium [Sc]
• CPC Class Codes: H01L 2924/12041 LED
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

An embodiment of the invention provides a chip package which includes a substrate having an upper surface and a lower surface and having at least a side surface, and at least a trench extending from the upper surface towards the lower surface and extending from the side surface towards an inner portion of the substrate, wherein a width of the trench near the upper surface is not equal to a width of the trench near the lower surface, and at least an insulating layer located on a sidewall of the trench, and at least a conducting pattern located on the insulating layer, wherein the side surface is separated from the conducting pattern in the trench by a predetermined distance such that a portion of the insulating layer is exposed, and at least a conducting region electrically connected to the conducting pattern.

Claims

1. A chip package, comprising:

a substrate having an upper surface and a lower surface and having at least a side surface;

at least a trench extending from the upper surface towards the lower surface and extending from the side surface towards an inner portion of the substrate, wherein a width of the trench near the upper surface is not equal to a width of the trench near the lower surface;

at least an insulating layer located on a sidewall of the trench;

at least a conducting pattern located on the insulating layer, wherein the side surface is separated from the conducting pattern in the trench by a predetermined distance such that a portion of the insulating layer is exposed; and

at least a conducting region electrically connected to the conducting pattern.

2. The chip package as claimed in claim 1, further comprising:

at least a second trench extending from the upper surface towards the lower surface and extending from a second side surface of the substrate towards the inner portion of the substrate, wherein a width of the second trench near the upper surface is not equal to a width of the second trench near the lower surface;

at least a second insulating layer located on a sidewall of the second trench;

at least a second conducting pattern located on the second insulating layer, wherein the second side surface is separated from the second conducting pattern in the second trench by a second predetermined distance such that a portion of the second insulating layer is exposed; and

at least a second conducting region electrically connected to the second conducting pattern.

3. The chip package as claimed in claim 2, further comprising a chip disposed on the substrate, wherein the conducting region and the second conducting region are located on the chip.

4. The chip package as claimed in claim 3, wherein the chip comprises a light emitting chip.

5. The chip package as claimed in claim 2, further comprising:

at least a third trench extending from the upper surface towards the lower surface and extending from a third side surface of the substrate towards the inner portion of the substrate, wherein a width of the third trench near the upper surface is not equal to a width of the third trench near the lower surface;

at least a third insulating layer located on a sidewall of the third trench;

at least a third conducting pattern located on the third insulating layer, wherein the third side surface is separated from the third conducting pattern in the third trench by a third predetermined distance such that a portion of the third insulating layer is exposed; and

at least a third conducting region electrically connected to the third conducting pattern.

6. The chip package as claimed in claim 5, wherein the substrate comprises a semiconductor substrate.

7. The chip package as claimed in claim 6, further comprising:

a drain region located in the semiconductor substrate, wherein a conductivity type of the drain region is a first conductivity type;

a doped region located in the semiconductor substrate, wherein a conductivity type of the doped region is a second conductivity type;

a source region located in the doped region, wherein a conductivity type of the source region is the first conductivity type; and

a gate located on the semiconductor substrate or buried in the semiconductor substrate, wherein the gate is separated from the semiconductor substrate by a gate dielectric layer, and wherein;

the drain region comprises the conducting region;

the source region comprises the second conducting region; and

the gate comprises the third conducting region.

8. The chip package as claimed in claim 7, wherein at least two of the side surface, the second side surface, and the third side surface are different side surfaces or a same side surface.

9. The chip package as claimed in claim 2, wherein the side surface and the second side surface are different side surfaces or a same side surface.

10. The chip package as claimed in claim 1, further comprising a printed circuit board having at least a pad, wherein the substrate is disposed on the printed circuit board, and the conducting pattern is electrically connected to the pad.

11. A method for forming a chip package, comprising:

providing a wafer comprising a plurality of regions defined by a plurality of predetermined scribe lines;

forming a plurality of through-holes penetrating through an upper surface and a lower surface of the wafer on locations overlapping the predetermined scribe lines, wherein a width of one of the trenches near the upper surface is not equal to a width of one of the trenches near the lower surface;

forming an insulating layer on sidewalls of the through-holes;

forming a conducting material layer on the insulating layer;

patterning the conducting material layer into a plurality of isolated conducting patterns separated from each other, wherein the conducting patterns do not contact with the predetermined scribe lines;

electrically connecting each of the conducting patterns to a corresponding conducting region; and

dicing the wafer along the predetermined scribe lines to form a plurality of chip packages.

12. The method for forming a chip package as claimed in claim 11, wherein the forming of the conducting patterns comprises:

forming a seed layer on the insulating layer in the through-holes;

forming a patterned electroplated photoresist layer on the seed layer, wherein the patterned electroplated photoresist layer covers a portion of the seed layer such that a portion of the seed layer not contacting with the predetermined scribe lines is exposed;

forming an electroplated conducting layer on the exposed seed layer and the patterned electroplated photoresist layer;

removing the patterned electroplated photoresist layer such that a portion of the seed layer contacting with the predetermined scribe lines and under the patterned electroplated photoresist layer is exposed; and

after the patterned electroplated photoresist layer is removed, removing the exposed seed layer to form the conducting patterns.

13. The method for forming a chip package as claimed in claim 12, wherein the patterned electroplated photoresist layer is a negative photoresist.

14. The method for forming a chip package as claimed in claim 13, wherein the forming of the patterned electroplated photoresist layer comprises:

forming an electroplated photoresist layer on the seed layer in the through-holes;

shielding two sides of an opening of each of the through-holes, respectively, such that the predetermined scribe lines are exposed;

irradiating the through-holes with a light such that a portion of the electroplated photoresist layer near the predetermined scribe lines is hardened; and

removing the electroplated photoresist layer which is not irradiated with the light to form the patterned electroplated photoresist layer.

15. The method for forming a chip package as claimed in claim 12, wherein when the patterned electroplated photoresist layer is removed, a portion of the electroplated conducting layer directly on the patterned electroplated photoresist layer is simultaneously removed.

16. The method for forming a chip package as claimed in claim 12, wherein during the step of removing the exposed seed layer, a portion of the electroplated conducting layer is simultaneously removed such that a thickness of the electroplated conducting layer is reduced.

17. The method for forming a chip package as claimed in claim 11, further comprising disposing a plurality of chips on the regions of the wafer, wherein each of the chips comprises the conducting region.

18. The method for forming a chip package as claimed in claim 11, wherein the wafer comprises a semiconductor wafer.

19. The method for forming a chip package as claimed in claim 18, wherein the semiconductor wafer comprises a plurality of power MOSFET elements.

20. The method for forming a chip package as claimed in claim 11, wherein the step of dicing the wafer is performed by using a dicing blade, and during the step of dicing the wafer along the predetermined scribe lines, the dicing blade does not directly contact with the conducting patterns.