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CHIP PACKAGE AND METHOD FOR FORMING THE SAME

  • US 20110248310A1
  • Filed: 04/06/2011
  • Published: 10/13/2011
  • Est. Priority Date: 04/07/2010
  • Status: Active Grant
First Claim
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1. A chip package, comprising:

  • a substrate having an upper surface and a lower surface and having at least a side surface;

    at least a trench extending from the upper surface towards the lower surface and extending from the side surface towards an inner portion of the substrate, wherein a width of the trench near the upper surface is not equal to a width of the trench near the lower surface;

    at least an insulating layer located on a sidewall of the trench;

    at least a conducting pattern located on the insulating layer, wherein the side surface is separated from the conducting pattern in the trench by a predetermined distance such that a portion of the insulating layer is exposed; and

    at least a conducting region electrically connected to the conducting pattern.

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