CROSS-FEEDBACK PHASE-LOCKED LOOP FOR DISTRIBUTED CLOCKING SYSTEMS

• US 20110248755A1
• Filed: 04/08/2010
• Published: 10/13/2011
• Est. Priority Date: 04/08/2010
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Munshi, Kambiz R., Franza, Olivier, Hasenplaugh, William C.
• Application Number:
  US12/756,979
• Publication Number:
  US 20110248755A1
• Time in Patent Office: Days
• US Class Current: 327/157
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop

Abstract

According to various embodiments, a cross-feedback phase-locked loop (XF-PLL) may include a secondary phase/frequency detector to detect the phase/frequency differences between two adjacent domains and feed the phase/frequency differences back into the main feedback loop of the XF-PLL, thereby reducing accumulated jitter and inter-domain clock skew in a distributed clocking system. Other embodiments may be described and claimed.

Claims

1. An apparatus comprising:

a first domain having a first phase-locked loop (PLL);

a second domain having a second PLL, the second domain being adjacent to the first domain, wherein

the first PLL is configured to receive a first input from an output of the first PLL and a second input from an output of the second PLL, and

the second PLL is configured to receive a third input from the output of the first PLL and a fourth input from the output of the second PLL to form a cross feedback relationship between the first PLL and the second PLL.

2. The apparatus of claim 1, wherein the first PLL further comprises:

a main phase or frequency detector configured to receive the first input;

a main charge pump and a voltage controlled oscillator (VCO) coupled to the main phase or frequency detector to form a main feedback loop; and

a first secondary phase or frequency detection unit coupled to the main feedback loop, the first secondary phase or frequency detection unit configured to receive the second input and the output of the first PLL.

3. The apparatus of claim 2, wherein the output of the first PLL is coupled to the second PLL of the second domain via another secondary phase or frequency detector unit coupled to the second PLL.

4. The apparatus of claim 2, wherein the first secondary phase or frequency detector unit comprises a secondary phase/frequency detector and a secondary charge pump.

5. The apparatus of claim 2, wherein the first secondary phase or frequency detector unit comprises a lead/lag detector configured to cause the main charge pump to increase or decrease a current by a predefined amount.

6. The apparatus of claim 2, wherein the first secondary phase or frequency detector unit is configured to be disabled during initial locking period of the first PLL.

7. The apparatus of claim 2, wherein the first secondary phase or frequency detector unit comprises a phase detector.

8. The apparatus of claim 4, wherein the secondary charge pump is structurally similar to the main charge pump and configured to produce a fraction of a current compared to the main charge pump.

9. The apparatus of claim 2, wherein the first PLL further comprises:

a second secondary phase or frequency detection unit coupled to the main feedback loop, the second secondary phase or frequency detection unit configured to receive the output of the first PLL and an output from a third PLL of a third domain to form a cross feedback relationship with the third domain, the third domain being adjacent to the first domain.

10. The apparatus of claim 1, wherein the apparatus is a multi-core microprocessor comprising a plurality of domains with a one-dimensional or two-dimensional layout.

11. A method comprising:

receiving, by a secondary phase frequency detector unit disposed on an integrated circuit comprising multiple domains, a first input signal based on an output of a main phase-locked loop (PLL) of a first domain and a second input signal based on an output of a second PLL of a second domain, the second domain being adjacent to the first domain;

detecting, by the secondary phase or frequency detection unit, a phase or frequency difference between the first and the second input signal; and

adjusting the output of the main PLL at least partially based on detected phase or frequency difference.

12. The method of claim 11, wherein the adjusting the output of the main PLL further comprising adjusting an output of a main charge pump of the main PLL at least partially based on the detected phase or frequency difference.

13. The method of claim 11, wherein the secondary phase or frequency detector unit comprises a lead/lag detector, and the main PLL comprises a charge pump, and the method further comprising:

increasing or decreasing an output of the charge pump by a predefined amount at least partially based on whether a phase/frequency of the first input signal is leading or lagging with respect to the second input signal.

14. The method of claim 11, further comprising:

disabling the secondary phase/frequency detector unit during initial locking period of the main PLL.

15. The method of claim 11, wherein the secondary phase or frequency detector unit comprises a secondary charge pump, and the method further comprising:

adjusting an output of the secondary charge pump based on a secondary charge pump v. main charge pump current ratio.

16. A system comprising:

a memory controller disposed on a die;

a plurality of execution units disposed on a die coupled to the memory controller, wherein respective ones of the plurality of execution units are adjacent to one or more neighboring executing units and the respective ones of the plurality of execution units further comprise a cross-feedback phase-locked loop (XF-PLL) configured to receive a main input from an output of the XF-PLL and one or more secondary inputs respectively from one or more outputs of one or more XF-PLL'"'"'s of the corresponding one or more neighboring execution units.

17. The system of claim 16, wherein the XF-PLL further comprises:

a main phase or frequency detector configured to receive the main input;

a main charge pump and a voltage controlled oscillator (VCO) coupled to the main phase or frequency detector to form a main feedback loop;

one or more secondary phase or frequency detector units coupled to the main feedback loop, the one or more secondary phase or frequency detector configured to respectively receive the one or more secondary inputs.

18. The system of claim 17, wherein the one or more secondary phase or frequency detectors are configured to receive an output of the VCO.

19. The system of claim 17, wherein respective ones of the one or more secondary phase or frequency detector units comprise a secondary phase/frequency detector and a secondary charge pump.

20. The system of claim 17, wherein respective ones of the one or more secondary phase or frequency detector units comprise a lead/lag detector configured to cause the main charge pump to increase or decrease a current by a predefined amount.

21. The system of claim 17, wherein respective ones of the one or more secondary phase or frequency detector units comprise a phase detector.

22. The system of claim 19, wherein respective ones of the secondary charge pump is structurally similar to the main charge pump and configured to produce a fraction of a current compared to the main charge pump.