DATA REPRODUCTION CIRCUIT
First Claim
1. A data reproduction circuit for receiving data and reproducing data and a clock, comprising;
- a first clock generation circuit for generating a clock for over-sampling data, based on a reference clock;
an over-sampling determination circuit for sampling the received data by a clock with a frequency higher than a data rate of the received data, based on a clock generated by a first clock generation circuit and converting it into digital signals;
a data selection circuit with a circuit for selecting and outputting a reproduced data by determining the digital signals generated by the over-sampling determination circuit in a timing based on the first reproduced clock, a phase/frequency error detection circuit for detecting a phase error and a frequency error from a timing difference with the received data, based on the first reproduced clock and a circuit for outputting a signal for adjusting a phase and a frequency, based on an output of the phase/frequency error detection circuit; and
a second clock generation circuit with a frequency adjustment circuit in which the adjustment signal reflects phase adjustment of a second reproduced clock in a state at least immediately before the first reproduced clock and adjustment of the frequency error and which generates the first reproduced clock and a circuit for supplying the first reproduced clock to the over-sampling determination circuit and the data selection circuit.
1 Assignment
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Accused Products
Abstract
This is a data reproduction circuit for receiving data and reproducing the data and its clock which has an over-sampling determination circuit for sampling the received data by a clock with frequency higher than the data rate of the received data and converting the sampled data into digital signals, a circuit for selecting and outputting the reproduced data, a phase error detection circuit for detecting a phase error from its timing deviation with the received data, based on the reproduced clock, a data selection circuit for adjusting its phase, based on the output of the phase error detection circuit, a phase adjustment circuit for adjusting the phase of the reproduced clock to reproduce a new clock and a clock generation circuit for supplying the over-sampling determination circuit and the data selection circuit with the newly reproduced clock.
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Citations
8 Claims
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1. A data reproduction circuit for receiving data and reproducing data and a clock, comprising;
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a first clock generation circuit for generating a clock for over-sampling data, based on a reference clock; an over-sampling determination circuit for sampling the received data by a clock with a frequency higher than a data rate of the received data, based on a clock generated by a first clock generation circuit and converting it into digital signals; a data selection circuit with a circuit for selecting and outputting a reproduced data by determining the digital signals generated by the over-sampling determination circuit in a timing based on the first reproduced clock, a phase/frequency error detection circuit for detecting a phase error and a frequency error from a timing difference with the received data, based on the first reproduced clock and a circuit for outputting a signal for adjusting a phase and a frequency, based on an output of the phase/frequency error detection circuit; and a second clock generation circuit with a frequency adjustment circuit in which the adjustment signal reflects phase adjustment of a second reproduced clock in a state at least immediately before the first reproduced clock and adjustment of the frequency error and which generates the first reproduced clock and a circuit for supplying the first reproduced clock to the over-sampling determination circuit and the data selection circuit. - View Dependent Claims (2, 8)
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3. A data reproduction circuit for receiving data and reproducing data and a clock, comprising;
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a clock generation circuit for generating a clock for over-sampling the received data, based on a reference clock; an over-sampling determination circuit for sampling the received data by a clock with a frequency higher than a data rate of the received data and converting it into digital signals; a data selection circuit with a circuit for selecting and outputting reproduced data by determining the digital signals generated by the over-sampling determination circuit, based on a first reproduced clock and a circuit for generating a signal for controlling a second reproduced clock for generating the first reproduced clock; a clock selection circuit for selecting the second reproduced clock by the clock supplied by the clock generation circuit and the control signal; and a phase-locked loop (PLL) circuit for reducing the jitters of the second reproduced clock and generating the first reproduced clock. - View Dependent Claims (4, 5, 6)
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7. A data reproduction circuit for receiving data and reproducing data and a clock, comprising;
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a determination clock generation circuit for generating a clock for over-sampling the received data, based a reference clock; an over-sampling determination circuit for sampling the received data by a clock with a frequency higher than a data rate of the received data, based on a sample clock generated by the determination clock generation circuit and converting it into digital signals; a writing control circuit for adjusting a timing of the sample clock from the determination clock generation circuit; a first selector circuit for writing and controlling the digital signals into a plurality of buffers, based on an output of the writing control circuit; a second selector circuit for reading the digital signals from the buffers by a reading signal which selects the digital signals; a data selection clock generation circuit for generating a reproduced clock for reproducing the data; a reading control circuit for controlling the reading signal, based on the reproduced clock generated by the data selection clock generation circuit; and a data selection circuit for selecting and outputting reproduced data by determining the digital signals selected and outputted by the second selector circuit at a timing based on the reproduced clock.
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Specification