SYSTEM AND METHOD FOR OPERATING A NON-VOLATILE MEMORY INCLUDING A PORTION OPERATING AS A SINGLE-LEVEL CELL MEMORY AND A PORTION OPERATING AS A MULTI-LEVEL CELL MEMORY

• US 20110252187A1
• Filed: 03/23/2011
• Published: 10/13/2011
• Est. Priority Date: 04/07/2010
• Status: Abandoned Application

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Inventors: Bar, Ilan, SEGAL, Avigdor, Barsky, Boris, Maly, Igal
• Application Number:
  US13/070,245
• Publication Number:
  US 20110252187A1
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels

Abstract

System and method for storing data in a non-volatile memory including a multi-level cell and single-level cell memory portions. To write a dataset to the non-volatile memory, if the size of the dataset is equal to the size of pages in the multi-level cell memory portion, the dataset may be written directly to the multi-level cell memory portion to fill an integer number of pages in a single write operation. However, if the size of the dataset is different than the size of the multi-level cell memory pages, at least a portion of the dataset may be temporarily written to the single-level cell memory portion until data is accumulated in a plurality of write operations having a size equal the size of the multi-level cell memory pages. The accumulated data may fill an integer number of the pages in the multi-level cell memory portion in a single write operation.

Claims

1. A device comprising:

a non-volatile memory including a portion operating as a multi-level cell memory storing data in pages and a portion operating as

a single-level cell memory electrically connected to the multi-level cell memory portion; and

a processor to receive an instruction to write a dataset to the non-volatile memory, wherein if the size of the dataset is equal to the size of an integer number of the pages, the processor writes the dataset directly to the multi-level cell memory portion to fill an integer number of the pages in the multi-level cell memory portion in a single write operation and wherein if the size of the dataset is different than the size of an integer number of the pages, the processor writes at least a portion of the dataset temporarily to the single-level cell memory portion until data is accumulated in a plurality of write operations to the single-level cell memory portion having a size equal the size of an integer number of the pages and the processor writes the accumulated data from the single-level cell memory portion to fill an integer number of the pages in the multi-level cell memory portion in a single write operation.

2. The device of claim 1, wherein if the size of the dataset is smaller than the size of one of the pages, the processor writes the entire dataset to the single-level cell memory portion.

3. The device of claim 1, wherein if the size of the dataset is larger than the size of the page, the processor writes a portion of the dataset equal to the size of one or more pages directly to the multi-level cell memory portion and a remaining portion of the dataset smaller than the size of the page to the single-level cell memory portion.

4. The device of claim 1, wherein the single-level cell memory portion stores data in pages the same size as the pages of the multi-level cell memory portion.

5. The device of claim 4, wherein when a plurality of partial write operations, each partially filling a page in the single-level cell memory portion, together completely fill the page in the single-level cell memory portion, the processor writes the entire page in a single write operation from the single-level cell memory portion to a page in the multi-level cell memory portion.

6. The device of claim 1, wherein the pages have a predetermined size.

7. The device of claim 1, comprising a plurality of single-level cell memory blocks each independently storing data in the multi-level cell memory portion.

8. The device of claim 7, comprising a plurality of multi-level cell buffer blocks each independently storing data directly in the multi-level cell memory portion.

9. The device of claim 8, comprising an equal number of single-level cell memory blocks and multi-level cell buffer blocks, wherein each single-level cell memory block is independently connected to a unique multi-level cell buffer block.

10. The device of claim 1, wherein the single-level cell memory portion is a cache memory.

11. The device of claim 1, wherein the non-volatile memory is a flash memory unit.

12. A method comprising:

receiving an instruction to write a dataset to a non-volatile memory including a portion operating as a multi-level cell memory and a portion operating as a single-level cell memory, wherein data is written to the multi-level cell memory in pages;

if the size of the dataset is equal to the size of an integer number of the pages, writing the dataset directly to the multi-level cell memory portion to fill an integer number of pages in the multi-level cell memory portion in a single write operation;

if the size of the dataset is different than the size of an integer number of the pages, writing at least a portion of the dataset temporarily to the single-level cell memory portion until data is accumulated in a plurality of write operations to the single-level cell memory portion having a size equal the size of an integer number of the pages; and

writing the accumulated data from the single-level cell memory portion to fill an integer number of the pages in the multi-level cell memory portion in a single write operation.

13. The method of claim 12, wherein if the size of the dataset is smaller than the size of one of the pages, the entire dataset is written to the single-level cell memory portion.

14. The method of claim 12, wherein if the size of the dataset is larger than the size of one of the pages, a portion of the dataset equal to the size of one or more pages is written directly to the multi-level cell memory portion and a remaining portion of the dataset smaller than the size of one page is written to the single-level cell memory portion.

15. The method of claim 12, wherein data is written to the single-level cell memory portion in pages the same size as the pages of the multi-level cell memory portion.

16. The method of claim 15, wherein when a plurality of partial write operations, each partially filling a page in the single-level cell memory portion, together completely fill the page in the single-level cell memory portion, the entire page is written in a single write operation from the single-level cell memory portion to a page in the multi-level cell memory portion.

17. The method of claim 12, wherein the pages in the multi-level cell memory portion have a predetermined size.

18. The method of claim 12, wherein data written from the single-level cell memory portion to the multi-level cell memory portion are aligned with the pages of the multi-level cell memory portion.

19. A system for storing data, comprising:

a multi-level cell (MLC) memory;

a plurality of single-level cell (SLC) cache blocks electrically connected to the MLC memory;

a plurality of ports electrically connected to the plurality of SLC cache blocks; and

a processor to write a plurality of streams of data via the ports to each partially fill two or more pages of the SLC cache blocks, to merge the data from the plurality of streams of data to completely fill one or more merged pages of the SLC cache blocks and to write each of the merged pages of the SLC cache blocks to completely fill a page in the MLC memory in a single operation.

20. The system of claim 19, wherein the data stored in two or more write operations to partially fill the two or more pages of the SLC cache blocks are stored in fewer write operations to completely fill a fewer number of pages in the MLC memory.