Narrow Graphene Nanoribbons from Carbon Nanotubes

• US 20110253969A1
• Filed: 04/15/2010
• Published: 10/20/2011
• Est. Priority Date: 04/15/2010
• Status: Active Grant

• Current Assignee: Board of Trustees of the Leland Stanford Junior University (Stanford University)
• Original Assignee: Board of Trustees of the Leland Stanford Junior University (Stanford University)
• Inventors: Jiao, Liying, Dai, Hongie
• Granted Patent: US 8,236,626 B2
• Time in Patent Office: Days
• US Class Current: 257/9
• CPC Class Codes: B82Y 30/00 Nanotechnology for materials or surface science, e.g. nanocomposites
• CPC Class Codes: B82Y 40/00 Manufacture or treatment of nanostructures
• CPC Class Codes: H01L 29/1606 Graphene
• CPC Class Codes: H10K 10/484 characterised by the channel regions
• CPC Class Codes: Y10S 977/848 Tube end modifications, e.g. capping, joining, splicing
• CPC Class Codes: Y10S 977/882 Assembling of separate components, e.g. by attaching
• CPC Class Codes: Y10S 977/888 Shaping or removal of materials, e.g. etching
• CPC Class Codes: Y10S 977/89 Deposition of materials, e.g. coating, cvd, or ald
• CPC Class Codes: Y10S 977/936 in a transistor or 3-terminal device

Abstract

Disclosed is a method for making graphene nanoribbons (GNRs) by controlled unzipping of structures such as carbon nanotubes (CNTs) by etching (e.g., argon plasma etching) of nanotubes partly embedded in a polymer film. The GNRs have smooth edges and a narrow width distribution (2-20 nm). Raman spectroscopy and electrical transport measurements reveal the high quality of the GNRs. Such a method of unzipping CNTs with well-defined structures in an array will allow the production of GNRs with controlled widths, edge structures, placement and alignment in a scalable fashion for device integration. GNRs may be formed from nanostructures in a controlled array to form arrays of parallel or overlapping structures. Also disclosed is a method in which the CNTs are in a predetermined pattern that is carried over and transferred to a substrate for forming into a semiconductor device.

Claims

1. A method for producing a graphene nanoribbon by opening a closed carbon nanostructure (“

CNS”

), comprising the steps of;

(a) depositing a CNS onto a first substrate;

(b) applying a protective coating to cover the CNS on the first substrate;

(c) obtaining an exposed strip along the CNS essentially free of protective coating;

(d) treating said exposed strip along the CNS to remove outer wall bonds in said exposed strip to produce an etched CNS; and

(e) recovering the etched CNS from the protective coating to produce the graphene nanoribbon from one or more outer walls having bonds removed.

2. The method of claim 1 wherein the step of obtaining an exposed strip comprises separating the CNS from the substrate

3. The method of claim 1 wherein said CNS is selected from the group consisting of MWNT, SWNT, spherical fullerenes, carbon nano-onions, carbon nanohorns, carbon helicoidal tubes, and carbon toroidal structures.

4. The method of claim 2 wherein said CNS is an MWNT.

5. The method of claim 1 wherein said graphene nanoribbon has between one and four layers.

6. The method of claim 1 wherein said graphene nanoribbon has ultrasmooth edges.

7. The method of claim 1 wherein graphene nanoribbon has a width between about 10 nm and 20 nm.

8. The method of claim 1 wherein said depositing a CNS onto a substrate comprises applying a dispersed mixture of CNS onto a substrate.

9. The method of claim 1 wherein said protective coating is a polymer.

10. The method of claim 9 wherein said polymer is an acrylate selected from the group consisting of polyacrylamides, polycarbonates, silicone, or co- and terpolymers of acrylates.

11. The method of claim 10 wherein the polymer is poly (methyl methacrylate).

12. The method of claim 1 wherein said treating said exposed strip comprises contacting the exposed strip with a plasma.

13. The method of claim 12 wherein the plasma is argon plasma.

14. The method of claim 12 wherein the plasma is a low power plasma.

15. The method of claim 1 further comprising the step of treating said exposed strip for longer times to produce fewer layer graphene nanoribbons.

16. The method of claim 1 further comprising the step of removing the CNS, along with the protective coating, from the first substrate and applying it to a second substrate prior to said treating.

19. The method of claim 16 further comprising the step of fabricating a field effect transistor.

20. The method of claim 16 wherein resistivity of said graphene nanoribbon is between 10 and 40 kΩ

.

17. A method for producing a graphene nanoribbon device comprising the steps of:

(a) depositing a closed graphene nanostructure (hereinafter “

CNS”

) onto a first substrate;

(b) applying a protective coating to cover the CNS on the first substrate;

(c) separating the CNS from the substrate leaving an exposed strip along the CNS essentially free of protective coating;

(d) treating, optionally on a second substrate, said exposed strip to remove outer wall bonds in said exposed strip to produce an etched CNS;

(e) recovering the etched CNS from the protective coating to produce the graphene nanoribbon from one or more outer walls having bonds removed; and

(f) applying a recovered graphene nanoribbon to an electronic device.

18. The method of claim 17 wherein the step of applying the recovered graphene nanoribbon to lengthwise on a gate material between a source electrode at one end portion and a drain electrode at an opposite end portion.

21. A method of preparing a graphene nanoribbon array, comprising the steps of:

(a) depositing a plurality of closed graphene nanostructures (“

CNSs”

) onto a first substrate in a predetermined pattern;

(b) applying a protective coating to cover the plurality of CNSs on the first substrate;

(c) separating the CNSs from the substrate leaving an exposed strip essentially free of protective coating and the CNSs embedded in said protective coating in said predetermined pattern;

(d) treating, optionally on a second substrate, said exposed strip to remove outer wall bonds in said exposed strip to produce etched CNSs embedded in said protective coating in said predetermined pattern; and

(e) transferring said etched CNSs embedded in said protective coating in said predetermined pattern to a third substrate in graphene nanoribbon array.

22. The method of claim 21 further comprising the step of forming an electronic device on said third substrate.

23. The method of claim 21 wherein said CNS is selected from the group consisting of SWNT and MWNT.

24. The method of claim 21 wherein said third substrate comprises a plurality of silicon back gates, one silicon backgate in contact with one graphene nanoribbon.

25. A semiconductor device having a number of transistors thereon, each transistor having a gate, drain and source terminal, wherein the transistors comprise a graphene nanoribbon connecting the source and drain terminals.