METHOD OF MANUFACTURING A VERTICAL TFET

• US 20110253981A1
• Filed: 04/08/2011
• Published: 10/20/2011
• Est. Priority Date: 04/19/2010
• Status: Active Grant

• Current Assignee: IMEC International, Katholieke Universiteit Leuven
• Original Assignee: IMEC International, Katholieke Universiteit Leuven
• Inventors: Vandooren, Anne, Leonelli, Daniele, Rooyackers, Rita, Loo, Roger, Verhulst, Anne S., De Gendt, Stefan
• Granted Patent: US 8,415,209 B2
• Time in Patent Office: Days
• US Class Current: 257/24
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/823885 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823821
• CPC Class Codes: H01L 29/0665 the shape of the body defining a nanostructure nanotechnology per se B82B
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/267 in different semiconductor regions , e.g. heterojunctions H01L29/263 takes precedence
• CPC Class Codes: H01L 29/66356 Gated diodes, e.g. field controlled diodes [FCD], static induction thyristors [SITh], field controlled thyristors [FCTh]
• CPC Class Codes: H01L 29/7391 Gated diode structures

Abstract

The present disclosure provides a method for manufacturing at least one nanowire Tunnel Field Effect Transistor (TFET) semiconductor device. The method comprises providing a stack comprising a layer of channel material with on top thereof a layer of sacrificial material, removing material from the stack so as to form at least one nanowire from the layer of channel material and the layer of sacrificial material, and replacing the sacrificial material in the at least one nanowire by heterojunction material. A method according to embodiments of the present disclosure is advantageous as it enables easy manufacturing of complementary TFETs.

Claims

1. A method for manufacturing a complementary nanowire tunnel field effect transistor semiconductor device, comprising:

providing a stack comprising a layer of sacrificial material atop a layer of channel material;

removing material from the layer of channel material and the layer of sacrificial material so as to form at least one first nanowire and at least one second nanowire;

forming a nanowire tunnel field effect transistor of a first dopant type by replacing the sacrificial material in the at least one first nanowire with heterojunction material of a first doping material of a first dopant type; and

thereafter

forming a nanowire tunnel field effect transistor of a second dopant type by replacing the sacrificial material in the at least one second nanowire with heterojunction material of a second doping material of a second dopant type, whereby a complementary nanowire tunnel field effect transistor device comprising at least one nanowire tunnel field effect transistor of the first dopant type and at least one nanowire tunnel field effect transistor of the second dopant type is obtained.

2. The method according to claim 1, wherein providing a stack comprises providing a layer of crystalline channel material.

3. The method according to claim 1, further comprising, after forming the nanowire tunnel field effect transistor, embedding the nanowire tunnel field effect transistor in insulating material.

4. The method according to claim 3, further comprising, before embedding the nanowire tunnel field effect transistor, covering the nanowire tunnel field effect transistor with a capping layer.

5. The method according to claim 4, wherein covering the nanowire tunnel field effect transistor with a capping layer comprises providing 20 atomic layers or less of semiconductor material.

6. The method according to claim 1, wherein replacing the sacrificial material comprises selectively etching back the sacrificial material.

7. The method according to claim 1, further comprising forming a gate stack around at least one of the first nanowire and the second nanowire.

8. The method according to claim 7, wherein replacing the sacrificial material is performed before forming the gate stack.

9. The method according to claim 7, wherein replacing the sacrificial material is performed after forming the gate stack.

10. A semiconductor device prepared according to the method of claim 1, the device comprising at least one vertical tunnel field effect transistor, the tunnel field effect transistor comprising a nanowire comprising a channel material and a heterojunction, wherein the nanowire is surrounded by a shell, at least at an interface between the channel material and the heterojunction.

11. The semiconductor device according to claim 10, wherein the semiconductor device comprises at least two vertical tunnel field effect transistors of different dopant types.