Hybrid Group IV/III-V Semiconductor Structures

• US 20110254052A1
• Filed: 09/16/2009
• Published: 10/20/2011
• Est. Priority Date: 10/15/2008
• Status: Abandoned Application

• Current Assignee: Arizona Board of Regents (University of Arizona)
• Original Assignee: Arizona Board of Regents (University of Arizona)
• Inventors: Menendez, Jose, Kouvetakis, John
• Application Number:
  US13/062,304
• Publication Number:
  US 20110254052A1
• Time in Patent Office: Days
• US Class Current: 257/190
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0245 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02452 including tin
• CPC Class Codes: H01L 21/02543 Phosphides
• CPC Class Codes: H01L 21/02546 Arsenides
• CPC Class Codes: H01L 21/02549 Antimonides
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 31/0324 comprising only AIVBVI or AIIBIVCVI chalcogenide compounds, e.g. Pb Sn Te
• CPC Class Codes: H01L 31/0687 Multiple junction or tandem solar cells
• CPC Class Codes: H01L 31/076 Multiple junction or tandem solar cells
• CPC Class Codes: H01L 31/105 the potential barrier being of the PIN type
• CPC Class Codes: H01L 31/1804 comprising only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 31/1844 comprising ternary or quaternary compounds, e.g. Ga Al As, In Ga As P
• CPC Class Codes: H01L 31/1852 comprising a growth substrate not being an AIIIBV compound
• CPC Class Codes: Y02E 10/544 Solar cells from Group III-V materials
• CPC Class Codes: Y02E 10/547 Monocrystalline silicon PV cells
• CPC Class Codes: Y02E 10/548 Amorphous silicon PV cells
• CPC Class Codes: Y02P 70/50 Manufacturing or production processes characterised by the final manufactured product

Abstract

Described herein are semiconductor structures comprising (i) a Si substrate; (ii) a buffer region formed directly over the Si substrate, wherein the buffer region comprises (a) a Ge layer having a threading dislocation density below about 10⁵ cm⁻²; or (b) a Ge_1-xSn_x layer formed directly over the Si substrate and a Ge_1-x-ySi_xSn_y layer formed over the Ge_1-xSn_x layer; and (iii) a plurality of III-V active blocks formed over the buffer region, wherein the first III-V active block formed over the buffer region is lattice matched or pseudomorphically strained to the buffer region. Further, methods for forming the semiconductor structures are provided and novel Ge_1-x-ySi_xSn_y, alloys are provided that are lattice matched or pseudomorphically strained to Ge and have tunable band gaps ranging from about 0.80 eV to about 1.4O eV.

Claims

1. A semiconductor structure comprising

(i) a Si substrate;

(ii) a buffer region formed directly over the Si substrate, wherein the buffer region comprises

(a) a Ge layer having a threading dislocation density below about 10⁵/cm², wherein the Ge layer is formed directly over the Si substrate;

or

(b) a Ge_1-xSn_x layer formed directly over the Si substrate and a Ge_1-x-ySi_xSn_y layer formed over the Ge_1-xSn_x layer; and

(iii) a plurality of III-V active blocks formed over the buffer region.

2. The semiconductor structure of claim 1, wherein the buffer region comprises a Ge layer having a threading dislocation density below 10⁵/cm².

3. The semiconductor structure of claim 2, wherein the Ge layer has a thickness of greater than about 5 μ

m.

4. The semiconductor structure of claim 2, wherein the Ge layer has a thickness of about 0.1 μ

m to about 1.0 μ

m.

5. The semiconductor structure of claim 1, wherein the buffer region comprises at least one active block.

6. The semiconductor structure of claim 1 wherein the buffer region comprises a first active block comprising the Ge layer having a threading dislocation density below 10⁵/cm², wherein the Ge layer is formed directly over the Si substrate.

7. The semiconductor structure of claim 6, wherein the buffer region further comprises a second active block comprising a Ge_1-x-ySi_xSn_y layer lattice matched or pseudomorphically strained to the first active block formed over the first active block.

8. The semiconductor structure of claim 7, wherein x and y for the Ge_1-x-ySi_xSn_y layer are in a ratio of about 3:

1 to about 5;

1.

9. The semiconductor structure of claim 7, wherein the Ge_1-x-ySi_xSn_y layer has a bandgap of about 0.80 eV to about 1.40 eV.

11. The semiconductor structure of claim 9 wherein the Ge_1-x-ySi_xSn_y layer comprises an alloy the formula, Ge_1-X(Si_β

Sn_1-β

)_X wherein β

is about 0.79 and X is a value greater than 0 and less than 1.

12. The semiconductor structure of claim 9 wherein the second active block comprises a Ge_1-x-ySi_xSn_y alloy, lattice matched or pseudomorphically strained to Ge, wherein x is about 0.07 to about 0.42 and y is about 0.01 to about 0.20.

14. The semiconductor structure of claim 1 wherein the buffer region comprises a Ge_1-xSn_x layer formed directly over the Si substrate and a Ge_1-x-ySi_xSn_y layer formed over the Ge_1-xSn_x layer.

15. The semiconductor structure of claim 14, wherein the buffer region comprises a Ge_1-xSn_x layer formed directly over the Si substrate and a first active block comprising the Ge_1-x-ySi_xSn_y layer formed over the Ge_1-xSn_x layer.

17. The semiconductor structure of claim 15 wherein the first active block comprises a p-n or p-i-n junction.

18. The semiconductor structure of claim 15 wherein the first active block comprises a Ge_1-x-ySi_xSn_y alloy, lattice matched or pseudomorphically strained to Ge, wherein x is about 0.19 to about 0.37 and y is about 0.02 to about 0.12.

19. The semiconductor structure of claim 15 wherein the first active block comprises a Ge_1-x-ySi_xSn_y alloy, lattice matched or pseudomorphically strained to Ge, having a bandgap of about 0.80 eV to about 1.40 eV.

20. The semiconductor structure of claim 15 wherein the first active block comprises a Si_0.075Ge_0.905Sn_0.02, Si_0.08Ge_0.90Sn_0.02, Si_0.19Ge_0.76Sn_0.05, Si_0.20Ge_0.745Sn_0.055, Si_0.23Ge_0.71Sn_0.06, Si_0.26Ge_0.67Sn_0.07, Si_0.30Ge_0.60Sn_0.10, Si_0.31Ge_0.60Sn_0.09, Si_0.32Ge_0.64Sn_0.04, or Si_0.41Ge_0.48Sn_0.11, Si_0.27Ge_0.56Sn_0.17 alloy, each lattice matched or pseudomorphically strained to the Ge layer.

21. The semiconductor structure of claim 14, wherein the buffer region comprises a first active block comprising the Ge_1-xSn_x layer formed directly over the Si substrate and a second active block comprising a Ge_1-x-ySi_xSn_y layer, wherein the second active block is formed over the first active block.

22. The semiconductor structure of claim 21, wherein the first active block and second active block independently comprise a p-n or p-i-n junction.

23. The semiconductor structure of claim 21 the Ge_1-xSn_x layer comprises a Ge_1-xSn_x alloy, wherein x is about 0.01 to about 0.20.

27. The semiconductor structure of claim 1 wherein each III-V active block comprises a p-n or p-i-n junction.

28. The semiconductor structure of claim 27, wherein each III-V active block comprises a binary, tertiary, quaternary, or higher (InGaAl)(AsSbP) semiconductor.

10. (canceled)

13. (canceled)

16. (canceled)

24. (canceled)

25. (canceled)

26. (canceled)

29. (canceled)

30. (canceled)

31. (canceled)

32. (canceled)

33. A method for forming a semiconductor structure comprising

forming a buffer region directly over a Si substrate;

and

forming a plurality of III-V active blocks over the buffer region, wherein the buffer region comprises

(a) a Ge layer having a threading dislocation density below 10⁵/cm² and a Ge_1-x-ySi_xSn_y layer formed over the Ge layer, wherein the Ge layer is formed directly over the Si substrate;

or

(b) a Ge_1-xSn_x layer and a Ge_1-x-ySi_xSn_y layer formed over the Ge_1-xSn_x layer, wherein the Ge_1-xSn_x layer is formed directly over the Si substrate.

34. The method of claim 33, wherein the buffer region and/or the plurality of III-V active blocks are each independently formed by source molecular beam epitaxy, chemical vapor deposition, plasma enhanced chemical vapor deposition, laser assisted chemical vapor deposition, and atomic layer deposition.

35. The method of claim 34, wherein each of the layers of the buffer region are prepared by CVD using digermane, silylgermane, trisilane, stannane, or mixtures thereof.

36. The method of claim 35, wherein the Si:

Sn concentration in each layer is tuned by reaction of trisilane and stannane as the sources of Si and Sn respectively.

37. (canceled)

38. (canceled)

40. The method of any one of claim 38 wherein the Ge_1-x-ySi_xSn_y layers are formed by contacting the Ge_1-xSn_x layer with a chemical vapor comprising (i) H₃SiGeH₃ or SiH₃SiH₂SiH₃;

and (ii) SnD₄.

39. (canceled)

41. A Ge_1-x-ySi_xSn_y alloy, lattice matched or pseudomorphically strained to Ge, wherein x is about 0.07 to about 0.42 and y is about 0.01 to about 0.20.

42. (canceled)

43. (canceled)

44. (canceled)

45. (canceled)

46. A Ge_1-x-ySi_xSn_y alloy, lattice matched or pseudomorphically strained to Ge, having a bandgap of about 0.80 eV to about 1.40 eV.

48. The Ge_1-x-ySi_xSn_y alloy of claim 46 wherein x is about 0.07 to about 0.42 and y is about 0.02 to about 0.20.

50. The Ge_1-x-ySi_xSn_y alloy of claim 48 wherein y is about 0.02 to about 0.12.

47. (canceled)

49. (canceled)

51. (canceled)

52. A GeSiSn alloy of the formula, Ge_1-X(Si_β

Sn_1-β

)_X wherein β

is about 0.79 and X is a value greater than 0 and less than 1.