STRUCTURES AND METHODS OF FABRICATING DUAL GATE DEVICES

• US 20110254084A1
• Filed: 03/02/2011
• Published: 10/20/2011
• Est. Priority Date: 03/02/2010
• Status: Active Grant

• Current Assignee: Vishay Siliconix
• Original Assignee: Vishay Siliconix
• Inventors: Bai, Yuming, Luo, Zhiyun, Pattanayak, Deva, Terrill, Kyle
• Granted Patent: US 9,577,089 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 21/31053 involving a dielectric removal step
• CPC Class Codes: H01L 21/3212 by chemical mechanical polishing [CMP]
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/4916 the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

First polysilicon (poly-1) is deposited into deep trenches that have been formed in a substrate. A first polysilicon polishing process is performed to planarize the exposed surfaces of the poly-1 so that the surfaces are flush with adjacent surfaces. Then, shallow trenches are formed in the substrate between the deep trenches, and second polysilicon (poly-2) is deposited into the shallow trenches. A second polysilicon polishing process is performed to planarize the exposed surface of the poly-2 so that the surface is flush with adjacent surfaces. Metal contacts to the poly-1 and the poly-2 are then formed.

Claims

1. A method of fabricating a dual gate semiconductor device, said method comprising:

depositing first polysilicon into a first trench and into a second trench that are formed in a substrate;

performing a first polysilicon polishing process to planarize exposed surfaces of said first polysilicon so that said surfaces are flush with adjacent surfaces;

after said first polysilicon polishing process, forming a third trench in said substrate between said first and second trenches, wherein said third trench is shallower than said first and second trenches;

depositing second polysilicon into said third trench;

performing a second polysilicon polishing process to planarize an exposed surface of said second polysilicon so that said surface is flush with adjacent surfaces; and

forming a first metal contact to said first polysilicon and a second metal contact to said second polysilicon.

2. The method of claim 1 further comprising:

prior to depositing said first polysilicon, depositing oxide into said first and second trenches and over said substrate between said first and second trenches; and

performing an oxide polishing process to planarize said oxide.

3. The method of claim 1 wherein said first and second polysilicon polishing processes and said oxide polishing process comprise chemical mechanical polishing processes.

4. The method of claim 1 wherein said first metal contact is directly over and in contact with said first polysilicon, and said second metal contact is directly over and in contact with said second polysilicon.

5. The method of claim 1 wherein said first metal contact is part of a first metal layer and said second metal contact is part of a second metal layer, wherein said first and second metal layers are in the same surface plane but are physically isolated from one another.

6. The method of claim 1 wherein said third trench is wider than said second metal contact.

7. A semiconductor device comprising:

a source trench formed in a substrate;

a gate trench formed in said substrate, wherein said gate trench is parallel to said source trench;

a source contact coupled to first polysilicon in said source trench at a first end of said source trench, wherein said source contact is directly over and in contact with a first surface of said first polysilicon; and

a gate contact coupled to second polysilicon in said gate trench at a second end of said gate trench, said second end opposite said first end, wherein said gate contact is directly over and in contact with a second surface of said second polysilicon.

8. The semiconductor device of claim 7 wherein said source contact is part of a first metal layer and said gate contact is part of a second metal layer, wherein said first and second metal layers are physically isolated from one another and in the same surface plane.

9. The semiconductor device of claim 7 wherein said gate trench is shallower than said source trench.

10. The semiconductor device of claim 7 wherein said first and second surfaces are both flush with a surface of a mesa formed by said gate and source trenches.

11. The semiconductor device of claim 10 wherein said source trench is lined with a first oxide layer and said gate trench is lined with a second oxide layer, wherein surfaces of said first and second oxide layers are flush with said first and second surfaces.

12. The semiconductor device of claim 7 wherein said gate trench is wider at said second end.

13. The semiconductor device of claim 7 wherein said gate trench is wider than said gate contact.

14. A method of fabricating a dual gate semiconductor device, said method comprising:

forming a first trench and a second trench in a substrate, said first and second trenches separated by a first mesa;

forming a first oxide layer inside said first and second trenches and over said first mesa, and then depositing first polysilicon into said first and second trenches;

performing a first polysilicon polishing process to remove at least some of said first polysilicon and an oxide polishing process to remove at least some of said first oxide layer from over said first mesa to form an even surface;

after said first polishing process and said oxide polishing process, forming a third trench in said first mesa between said first and second trenches, said first and third trenches separated by a second mesa and said second and third trenches separated by a third mesa, wherein said third trench is shallower than said first and second trenches;

forming a second oxide layer inside said third trench and over said second and third mesas, and then depositing second polysilicon into said third trench; and

performing a second polysilicon polishing process to remove at least some of said second polysilicon.

15. The method of claim 14 further comprising forming a first metal contact to said first polysilicon and a second metal contact to said second polysilicon.

16. The method of claim 15 wherein said first metal contact is directly over and in contact with said first polysilicon and said second metal contact is directly over and in contact with said second polysilicon in said second trench.

17. The method of claim 15 wherein said first metal contact is part of a first metal layer and said second metal contact is part of a second metal layer, wherein said first and second metal layers are in the same surface plane but are physically isolated from one another.

18. The method of claim 15 wherein said second metal contact is narrower than said third trench.

19. The method of claim 14 wherein said first and second polysilicon polishing processes and said oxide polishing process comprise chemical mechanical polishing processes.

20. The method of claim 14 wherein said oxide polishing process further comprises depositing additional oxide prior to oxide polishing.