SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

• US 20110254093A1
• Filed: 06/24/2010
• Published: 10/20/2011
• Est. Priority Date: 12/29/2009
• Status: Active Grant

• Current Assignee: Institute of Microelectronics Chinese Academy of Sciences
• Original Assignee: Institute of Microelectronics Chinese Academy of Sciences
• Inventors: Han, kai, Wang, Xiaolei, Wang, Wenwu, Chen, Dapeng, Chen, Shijie
• Granted Patent: US 8,222,099 B2
• Time in Patent Office: Days
• US Class Current: 257/368
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: Y10S 438/926 Dummy metallization

Abstract

A semiconductor device and a method of manufacturing the same are provided. A multi-component high-k interface layer containing elements of the substrate is formed from a ultra-thin high-k dielectric material in a single-layer structure of atoms by rapid annealing in the manufacturing of a CMOS transistor by the replacement gate process, and a high-k gate dielectric layer with a higher dielectric constant and a metal gate layer are formed thereon. The EOT of the device is effectively decreased, and the diffusion of atoms in the high-k gate dielectric layer from an upper level thereof is effectively prevented by the optimized high-k interface layer at high-temperature treatment. Thus, the present invention may also avoid the growth of the interface layers and the degradation of carrier mobility. Furthermore, the present invention may further alleviate the problem of high interface state and interface roughness caused by direct contact of the high-k gate dielectric layer with high dielectric constant and the substrate, and thus the overall performance of the device is effectively enhanced.

Claims

1. A method of manufacturing a semiconductor device, comprising;

a) providing a semiconductor substrate having a first region and a second region, wherein the first region and the second region are isolated from each other by an isolation region;

b) forming a dummy gate oxide layer, a dummy gate and a sidewall spacer thereof belonging to the first region and the second region on the semiconductor substrate, respectively, forming a source region and a drain region belonging to the first region and the second region in the semiconductor substrate, respectively, and forming an inner dielectric layer covering the source region and drain region of the first and second regions and the isolation region of the first and second regions;

c) removing the dummy gates of the first and second regions to form a first opening and a second opening;

d) forming, in the first opening and the second opening, a first high-k interface layer belonging to the first region and a second high-k interface layer belonging to the second region, respectively, wherein the first and second high-k interface layers contain elements of the substrate;

e) forming a first high-k gate dielectric layer on the first high-k interface layer, and forming a second high-k gate dielectric layer on the second high-k interface layer, wherein the dielectric constants of the first high-k gate dielectric layer and the second high-k gate dielectric layer are higher than those of the first and second high-k interface layers, respectively;

f) forming a first metal gate layer on the first high-k gate dielectric layer, and forming a second gate layer on the second high-k gate dielectric layer; and

g) processing the device to form a first gate stack belonging to the first region and a second gate stack belonging to a second region, respectively.

2. The method according to claim 1, wherein the step c) further comprises:

removing the dummy gate oxide layers of the first and second regions.

3. The method according to claim 1, wherein the first high-k interface layer and the second high-k interface layer are formed of elements selected from a group comprising:

HfO₂, ZrO₂, HfZrO_x, HfSiO_x, Al₂O₃, HfAlO_z, LaAlO_x, Gd₂O₃, and oxide, silicate and nitride of other rare earth, or any combination thereof.

4. The method according to claim 1, wherein the first and second high-k interface layers have a thickness in the range of about 0.1 nm-1 nm.

5. The method according to claim 1, wherein the step d) comprises:

depositing one or more layers of high-k dielectric material in a single-layer structure of atoms in the first opening and the second opening, respectively; and

performing annealing at high temperature to form the first and second high-k interface layers containing elements of the substrate on the substrate in the first and second openings.

6. The method according to claim 1, wherein the step d) comprises:

d1) depositing one or more layers of high-k dielectric material in a single-layer structure of atoms in the first opening and second opening, respectively;

d2) performing annealing at high temperature;

d3) repeating steps d1) and d2) to form a first high-k interface layer and a second high-k interface layer on the substrate in the first and second openings, wherein the first high-k interface layer and second high-k interface layer contain elements of the substrate.

7. The method according to claim 5, wherein the range of the high-temperature annealing is in the range from about 500°

C. to 950°

C., the time for the high-temperature annealing is in the range from about 1 second to 30 seconds, and the protective gas for the high-temperature annealing is N₂, NH₃ or O₂.

8. The method according to claim 6, wherein the range of the high-temperature annealing is in the range from about 500°

C. to 950°

C., the time for the high-temperature annealing is in the range from about 1 second to 30 seconds, and the protective gas for the high-temperature annealing is N₂, NH₃ or O₂.

9. The method according to claim 6, wherein the one or more layers of high-k material in a single-layer structure of atoms have a thickness in the range of about 0.1-0.3 nm.

10. The method according to claim 1, wherein the first and second high-k gate dielectric layers are formed of elements selected from a group comprising:

HfO₂, ZrO₂, HfSiO_x, HfZrO_x, HfON, HfSiON, HfAlO_x, Al₂O₃, ZrSiO_x, Ta₂O₅, La₂O₃, HfLaO_x, LaAlO_x, LaSiO_x, HfLaO_x, or HfLaON_x, or any combination thereof.

11. The method according to claim 1, wherein the first and second high-k gate dielectric layers have a thickness in the range of about 1-5 nm.

12. A semiconductor, comprising:

a semiconductor substrate having a first region and a second region, wherein the first region and the second region are isolated from each other by an isolation region;

a first gate stack formed on the first region, and a second gate stack formed on the second region; and

a source region and a drain region belonging to the first region and the second region, respectively;

wherein the first gate stack comprises;

a first high-k interface layer on the semiconductor substrate in the first region;

a first high-k gate dielectric layer on the first high-k interface layer; and

a first metal gate layer on the first high-k gate dielectric layer;

the second gate stack comprises;

a second high-k interface layer on the semiconductor substrate in the second region;

a second high-k gate dielectric layer on the second high-k interface layer; and

a second metal gate layer on the second high-k gate dielectric layer; and

the material of the first and second high-k interface layers comprises elements of the material of the substrate, and dielectric constants of the first and second high-k gate dielectric layers are higher than those of the first and second high-k interface layers, respectively.

13. The device according to claim 12, further comprising an interface layer between the first and second high-k interface layers and the substrate.

14. The device according to claim 12, wherein the first high-k interface layer and the second high-k interface layer are formed of elements selected from a group comprising:

HfO₂, ZrO₂, HfZrO_x, HfSiO_x, Al₂O₃, HfAlO_x, LaAlO_x, Gd₂O₃, and oxide, silicate and nitride of other rare earth, or any combination thereof.

15. The device according to claim 12, wherein the first and second high-k interface layers have a thickness in the range of about 0.1-1 nm.

16. The device according to claim 12, wherein the first and second high-k gate dielectric layers are selected from a group comprising:

HfO₂, ZrO₂, HfSiO_x, HfZrO_x, HfON, HfSiON, HfAlO_x, Al₂O₃, ZrSiO_x, Ta₂O₅, La₂O₃, HfLaO_x, LaAlO_x, LaSiO_x, HfLaO_x, or HfLaON_x, or any combination thereof.

17. The device according to claim 12, wherein the first and second high-k gate dielectric layers have a thickness in the range of about 1-5 nm.