Semiconductor Device and Method of Wafer Level Package Integration

• US 20110254156A1
• Filed: 06/29/2011
• Published: 10/20/2011
• Est. Priority Date: 12/03/2007
• Status: Active Grant

• Current Assignee: Stats Chippac Pte. Lte.
• Original Assignee: Stats Chippac Limited
• Inventors: Lin, Yaojian
• Granted Patent: US 9,460,951 B2
• Time in Patent Office: Days
• US Class Current: 257/737
• CPC Class Codes: H01L 21/566 Release layers for moulds, e.g. release layers, layers against residue during moulding
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68345 used as a support during the manufacture of self supporting substrates
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16237 the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48228 the bond pad being disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/81005 being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/81191 wherein the bump connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81815 Reflow soldering
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/3135 Double encapsulation or coating and encapsulation
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49822 : Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/15192 : Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/1532 : the connection portion being formed on the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30105 : Capacitance

Abstract

A method of making a wafer level chip scale package includes providing a temporary substrate, and forming a wafer level interconnect structure over the temporary substrate using wafer level processes. The wafer level processes include forming a first insulating layer in contact with an upper surface of the temporary substrate, and forming a first conductive layer in contact with an upper surface of the first passivation layer. A first semiconductor die is mounted over the wafer level interconnect structure such that an active surface of the first semiconductor die is in electrical contact with the first conductive layer, and a first encapsulant is deposited over the first semiconductor die. A second encapsulant is deposited over the first encapsulant, and the first and second encapsulants are cured simultaneously. The temporary substrate is removed to expose the first passivation layer.

Claims

1. A method of making a wafer level chip scale package, comprising:

providing a temporary substrate;

forming a wafer level interconnect structure over the temporary substrate using wafer level processes including forming a first insulating layer in contact with an upper surface of the temporary substrate, and forming a first conductive layer in contact with an upper surface of the first passivation layer;

mounting a first semiconductor die over the wafer level interconnect structure such that an active surface of the first semiconductor die is in electrical contact with the first conductive layer;

depositing a first encapsulant over the first semiconductor die;

depositing a second encapsulant over the first encapsulant;

curing the first and second encapsulants simultaneously;

removing the temporary substrate to expose the first passivation layer;

forming an under bump metallization (UBM) in electrical contact with the first conductive layer; and

forming conductive bumps on the UBM.

2. The method of claim 1, wherein mounting the first semiconductor die over the wafer level interconnect structure comprises:

forming a plurality of conductive bumps on a plurality of contact pads disposed on the active surface of the first semiconductor die;

contacting the conductive bumps of the first semiconductor die to the wafer level interconnect structure in a flip chip fashion; and

reflowing the conductive bumps.

3. The method of claim 2, wherein the conductive bumps comprise micro bumps.

4. The method of claim 1, wherein forming the wafer level interconnect structure comprises depositing the at least one conductive layer over the at least one insulating layer such that a bottom surface of the at least one conductive layer follows a contour defined by an upper surface and a sidewall of the at least one insulating layer.

5. The method of claim 1, wherein forming the wafer level interconnect structure comprises curing the at least one insulating layer at a temperature that is greater than or equal to 200°

C.

6. The method of claim 1, wherein forming the wafer level interconnect structure over the temporary wafer level substrate using wafer level processes further comprises forming a conductive multi-layer to contact an upper surface of the temporary wafer level substrate, the conductive multilayer including a wetting layer and an adhesive layer, the conductive multi-layer acting as contact pads.

7. The method of claim 6, wherein the conductive multilayer further includes a barrier layer disposed between the wetting layer and the adhesive layer.

8. A method of making a wafer level chip scale package, comprising:

providing a temporary wafer level substrate;

forming a wafer level interconnect structure over the temporary wafer level substrate using wafer level processes that include forming a first insulating layer over a top surface of the temporary wafer level substrate, and forming a first conductive layer over the first insulating layer;

mounting a first semiconductor die over the wafer level interconnect structure in electrical contact with the first conductive layer;

depositing a first encapsulant around the first semiconductor die;

removing the temporary wafer level substrate to expose a bottom surface of the first insulating layer; and

forming an interconnect structure in electrical contact with the first conductive layer.

9. The method of claim 8, wherein forming the interconnect structure comprises:

forming an under bump metallization (UBM) in electrical contact with the first conductive layer; and

forming conductive bumps on the UBM.

10. The method of claim 8, wherein depositing the first encapsulant comprises filling a gap between the first semiconductor die and the wafer level interconnect structure using a mold underfill process.

11. The method of claim 10, wherein the mold underfill process comprises blocking formation of the first encapsulant on side surfaces and a back surface of the first semiconductor die.

12. The method of claim 10, wherein the mold underfill process comprises injecting the second encapsulant in a liquid state into a chase mold.

13. The method of claim 12, further comprising drawing the second encapsulant into the gap between the first semiconductor die and the wafer level interconnect structure with a vacuum assist.

14. The method of claim 10, wherein depositing the first encapsulant further comprises filling a space over the first semiconductor die with the first encapsulant.

15. A method of making a wafer level chip scale package, comprising:

providing a temporary wafer level substrate;

forming a wafer level interconnect structure over the temporary wafer level substrate using wafer level processes that include forming a first insulating layer on a top surface of the temporary wafer level substrate, and forming a first conductive layer over the first insulating layer;

mounting a first semiconductor die over the wafer level interconnect structure in electrical contact with the first conductive layer; and

depositing a first encapsulant around the first semiconductor die.

16. The method of claim 15, wherein mounting the first semiconductor die comprises:

forming a plurality of conductive bumps on a plurality of contact pads disposed on an active surface of the first semiconductor die; and

contacting the conductive bumps of the first semiconductor die to the wafer level interconnect structure in a flip chip fashion.

17. The method of claim 16, wherein depositing the first encapsulant comprises disposing a no-flow underfill on the wafer level interconnect structure before mounting the first semiconductor die.

18. The method of claim 17, further comprising curing the no-flow underfill.

19. The method of claim 18, further comprising reflowing the conductive bumps after curing the no-flow underfill.

20. The method of claim 18, further comprising reflowing the conductive bumps during the curing of the no-flow underfill.

21. The method of claim 15, wherein forming the first insulating layer comprises applying the first insulating layer with a process selected from the group consisting of PVD, CVD, printing, spin coating, spray coating, sintering and thermal oxidation.

22. The method of claim 21, wherein applying the first insulating layer further comprises curing the first insulating layer at a temperature greater than or equal to 200 degrees C.

23. A semiconductor device, comprising:

a temporary wafer level substrate;

a wafer level interconnect structure disposed over the temporary wafer level substrate, the wafer level interconnect structure including a first insulating layer disposed over a top surface of the temporary wafer level substrate, and a first conductive layer disposed over the first insulating layer;

a first semiconductor die disposed over the wafer level interconnect structure and in electrical contact with the first conductive layer; and

a first encapsulant disposed around the first semiconductor die.

24. The semiconductor device of claim 23, further comprising:

contact pads disposed on an active surface of the first semiconductor die; and

conductive bumps disposed on the contact pads and electrically connecting the first semiconductor die to the wafer level interconnect structure.

25. The semiconductor device of claim 24, wherein the conductive bumps comprise micro bumps.