Semiconductor Device and Method of Wafer Level Package Integration
First Claim
1. A method of making a wafer level chip scale package, comprising:
- providing a temporary substrate;
forming a wafer level interconnect structure over the temporary substrate using wafer level processes including forming a first insulating layer in contact with an upper surface of the temporary substrate, and forming a first conductive layer in contact with an upper surface of the first passivation layer;
mounting a first semiconductor die over the wafer level interconnect structure such that an active surface of the first semiconductor die is in electrical contact with the first conductive layer;
depositing a first encapsulant over the first semiconductor die;
depositing a second encapsulant over the first encapsulant;
curing the first and second encapsulants simultaneously;
removing the temporary substrate to expose the first passivation layer;
forming an under bump metallization (UBM) in electrical contact with the first conductive layer; and
forming conductive bumps on the UBM.
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Accused Products
Abstract
A method of making a wafer level chip scale package includes providing a temporary substrate, and forming a wafer level interconnect structure over the temporary substrate using wafer level processes. The wafer level processes include forming a first insulating layer in contact with an upper surface of the temporary substrate, and forming a first conductive layer in contact with an upper surface of the first passivation layer. A first semiconductor die is mounted over the wafer level interconnect structure such that an active surface of the first semiconductor die is in electrical contact with the first conductive layer, and a first encapsulant is deposited over the first semiconductor die. A second encapsulant is deposited over the first encapsulant, and the first and second encapsulants are cured simultaneously. The temporary substrate is removed to expose the first passivation layer.
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Citations
25 Claims
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1. A method of making a wafer level chip scale package, comprising:
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providing a temporary substrate; forming a wafer level interconnect structure over the temporary substrate using wafer level processes including forming a first insulating layer in contact with an upper surface of the temporary substrate, and forming a first conductive layer in contact with an upper surface of the first passivation layer; mounting a first semiconductor die over the wafer level interconnect structure such that an active surface of the first semiconductor die is in electrical contact with the first conductive layer; depositing a first encapsulant over the first semiconductor die; depositing a second encapsulant over the first encapsulant; curing the first and second encapsulants simultaneously; removing the temporary substrate to expose the first passivation layer; forming an under bump metallization (UBM) in electrical contact with the first conductive layer; and forming conductive bumps on the UBM. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method of making a wafer level chip scale package, comprising:
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providing a temporary wafer level substrate; forming a wafer level interconnect structure over the temporary wafer level substrate using wafer level processes that include forming a first insulating layer over a top surface of the temporary wafer level substrate, and forming a first conductive layer over the first insulating layer; mounting a first semiconductor die over the wafer level interconnect structure in electrical contact with the first conductive layer; depositing a first encapsulant around the first semiconductor die; removing the temporary wafer level substrate to expose a bottom surface of the first insulating layer; and forming an interconnect structure in electrical contact with the first conductive layer. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A method of making a wafer level chip scale package, comprising:
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providing a temporary wafer level substrate; forming a wafer level interconnect structure over the temporary wafer level substrate using wafer level processes that include forming a first insulating layer on a top surface of the temporary wafer level substrate, and forming a first conductive layer over the first insulating layer; mounting a first semiconductor die over the wafer level interconnect structure in electrical contact with the first conductive layer; and depositing a first encapsulant around the first semiconductor die. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22)
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23. A semiconductor device, comprising:
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a temporary wafer level substrate; a wafer level interconnect structure disposed over the temporary wafer level substrate, the wafer level interconnect structure including a first insulating layer disposed over a top surface of the temporary wafer level substrate, and a first conductive layer disposed over the first insulating layer; a first semiconductor die disposed over the wafer level interconnect structure and in electrical contact with the first conductive layer; and a first encapsulant disposed around the first semiconductor die. - View Dependent Claims (24, 25)
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Specification