System and Method of Transistor Switch Biasing in a High Power Semiconductor Switch

• US 20110254614A1
• Filed: 04/16/2010
• Published: 10/20/2011
• Est. Priority Date: 04/16/2010
• Status: Active Grant

• Current Assignee: SIGE Semiconductor Incorporated (Skyworks Solutions Incorporated)
• Original Assignee: SIGE Semiconductor Incorporated (Skyworks Solutions Incorporated)
• Inventors: Huang, Chun-Wen Paul, Antognetti, Philip Michael, Doherty, Mark
• Granted Patent: US 8,093,940 B2
• Time in Patent Office: Days
• US Class Current: 327/534
• CPC Class Codes: H03K 17/063 in field-effect transistor switches
• CPC Class Codes: H03K 17/693 Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors logic circuits H03K19/00; code converters H03M5/00, H03M7/00
• CPC Class Codes: H03K 2217/0054 Gating switches, e.g. pass gates
• CPC Class Codes: H04B 1/44 Transmit/receive switching

Abstract

A system and method are provided for biasing transistor switches in a semiconductor based high power switch. Off-state Vgsd biasing for the off transistor switches is based upon acceptable levels of spurious harmonic emissions and linearity.

Claims

1. A method of biasing transistor switches in a high power switch, the method comprising:

providing on-state Vgsd (gate to source/drain bias voltage) at an on-state Vgsd level to a first transistor switch of said transistor switches for biasing the first transistor switch in an on state; and

providing off-state Vgsd at an off-state Vgsd level to a second transistor switch of said transistor switches for biasing the second transistor switch in an off state, wherein a magnitude of the off-state Vgsd level is less than a magnitude of the on-state Vgsd level by only an amount sufficient for at least one of;

bringing spurious harmonic emissions of said second transistor switch when biased to the off state below a pre-identified upper limit of acceptable spurious harmonic emissions from the second transistor switch in the off state; and

bringing a linearity of the high power switch above a pre-identified lower limit of acceptable linearity for the high power switch.

2. A method according to claim 1 further comprising:

identifying at least one of the upper limit of acceptable spurious harmonic emissions from the second transistor switch in the off state, and the lower limit of acceptable linearity for the high power switch.

3. A method according to claim 1 wherein the on-state Vgsd level is a maximum potential difference between gate and one of the source or drain within reliability and operating constraints of the transistor switches.

4. A method according to claim 1 wherein said off-state Vgsd level is a fixed fraction of said on-state Vgsd level.

5. A method according to claim 1 wherein said transistor switches are silicon-on-insulator FET switches, and wherein said on-state Vgsd level is between 2.0 V and 2.5 V, and wherein the off-state Vgsd level is between 1.1 V and 1.5 V.

6. A method according to claim 4 wherein providing the on-state Vgsd comprises biasing at a gate of the first transistor switch with an on-state gate voltage at a fixed primary biasing fraction of a high system control voltage and biasing at a source-drain of the first transistor switch with a on-state source-drain voltage at a fixed secondary biasing fraction of a low system control voltage, and wherein providing off-state Vgsd comprises biasing at a gate of the second transistor switch with a off-state gate voltage at the fixed primary biasing fraction of the low system control voltage and biasing at a source-drain of the second transistor switch with a off-state source-drain voltage at the fixed secondary biasing fraction of the high system control voltage.

7. A method according to claim 6, wherein the fixed primary biasing fraction and the fixed secondary biasing fraction of the high and low system control voltages are generated by voltage dividing the high and low system control voltages respectively.

8. A method according to claim 1 wherein the high power switch comprises an antenna, a first input/output terminal, and a second input/output terminal, wherein the first transistor switch is located along a first signal path from the antenna to the first input/output terminal, and the second transistor switch is located along a second signal path from the antenna to the second input/output terminal, and wherein the step of providing the on-state Vgsd to the first transistor switch is performed to provide a communication pathway between the antenna and the first input/output terminal, and the step of providing the off-state Vgsd to the second transistor switch is performed to isolate the antenna and the first input/output terminal from the second input/output terminal.

9. A method according to claim 8 further comprising:

providing on-state Vgsd at the on-state Vgsd level to the second transistor switch for biasing the second transistor switch in an on state; and

providing off-state Vgsd at the off-state Vgsd level to the first transistor switch for biasing the first transistor switch in an off state,

wherein the step of providing the on-state Vgsd to the second transistor switch is performed to provide a communication pathway between the antenna and the second input/output terminal, and the step of providing the off-state Vgsd to the first transistor switch is performed to isolate the antenna and the second input/output terminal from the first input/output terminal.

10. A method according to claim 1 wherein the high power switch comprises an antenna, a first input/output terminal, and a first ground connection, wherein the first transistor switch is located along a signal path from the first input/output terminal to the antenna, and the second transistor switch is located along a shunt path from the first input/output terminal to the first ground connection, and wherein the step of providing on-state Vgsd is performed to provide a communication pathway between the first input/output terminal and the antenna, and the step of providing off-state Vgsd is performed to isolate the antenna and the first input/output terminal from the first ground connection.

11. A method according to claim 10 wherein the high power switch comprises a second input/output terminal, and a third transistor switch of the transistor switches, wherein the third transistor switch is located along a signal path from the antenna to the second input/output terminal, wherein the step of providing the off-state Vgsd to the second transistor switch is performed in association with a step of:

providing off-state Vgsd at the off-state Vgsd level to the third transistor switch for biasing the third transistor switch in the off state,

and wherein the step of providing off-state Vgsd to the third transistor switch is performed to isolate the antenna and the first input/output terminal from the second input/output terminal.

12. A method according to claim 11 further comprising:

providing on-state Vgsd at the on-state Vgsd level to the second transistor switch for biasing the second transistor switch in an on state; and

providing off-state Vgsd at the off-state Vgsd level to the first transistor switch for biasing the first transistor switch in an off state, and

providing on-state Vgsd at the on-state Vgsd level to the third transistor switch for biasing the third transistor switch to an on state,

wherein the step of providing on-state Vgsd to the second transistor switch is performed to provide a shunt pathway between the first input/output terminal and the first ground connection, the step of providing on-state Vgsd to the third transistor switch is performed to provide a communication pathway between the second input/output terminal and the antenna, and the step of providing off-state Vgsd to the first transistor switch is performed to isolate the antenna and the second input/output switch from the first input/output terminal and the first ground connection.

13. A method according to claim 11 wherein the high power switch comprises a second ground connection and a fourth transistor switch of the transistor switches, wherein the fourth transistor switch is located along a signal path from the second input/output terminal to the second ground connection, wherein the step of providing off-state Vgsd to the second transistor switch is performed in association with a step of:

providing on-state Vgsd at the on-state Vgsd level to the fourth transistor switch for biasing the fourth transistor switch in the on state,

wherein the step of providing off-state Vgsd to the third transistor switch is performed also to isolate the antenna and the first input/output terminal from the second ground connection, and wherein the step of providing on-state Vgsd to the fourth transistor switch is performed to provide a shunt pathway from the second input/output terminal to the second ground connection.

14. A method according to claim 13 further comprising:

providing on-state Vgsd at the on-state Vgsd level to the second transistor switch for biasing the second transistor switch in an on state;

providing off-state Vgsd at the off-state Vgsd level to the first transistor switch for biasing the first transistor switch in an off state;

providing on-state Vgsd at the on-state Vgsd level to the third transistor switch for biasing the third transistor switch to an on state; and

providing off-state Vgsd at the off-state Vgsd level to the fourth transistor switch for biasing the fourth transistor switch in an off state,

wherein the step of providing on-state Vgsd to the second transistor switch is performed to provide a shunt pathway between the first input/output terminal and the first ground connection, wherein the step of providing on-state Vgsd to the third transistor switch is performed to provide a communication pathway between the second input/output terminal and the antenna, wherein the step of providing off-state Vgsd to the first transistor switch is performed to isolate the antenna and the second input/output terminal from the first input/output terminal and the first ground connection, and wherein the step of providing off-state Vgsd to the fourth transistor switch is performed to isolate the antenna and the second input/output switch from the second ground connection.

15. A method of biasing transistor switches in a high power switch, the method comprising:

biasing at a gate of a first transistor switch of the transistor switches with a first biasing controller at a fixed primary biasing fraction of a first control voltage input to the first biasing controller;

biasing at a source-drain of the first transistor switch with a second biasing controller at a fixed secondary biasing fraction of a second control voltage input to the second biasing controller;

biasing at a gate of a second transistor switch of the transistor switches with the second biasing controller at the fixed primary biasing fraction of the second control voltage input; and

biasing at a source-drain of the second transistor switch with the first biasing controller at the fixed secondary biasing fraction of the first control voltage;

wherein when the high power switch is in a first switch state in which the first transistor switch is on and the second transistor switch is off;

providing a high system control voltage as the first control voltage to the first basing controller; and

providing a low system control voltage as the second control voltage to the second biasing controller,

wherein when the high power switch is in a second switch state in which the first transistor switch is off and the second transistor switch is on;

providing a low system control voltage as the first control voltage to the first basing controller; and

providing a high system control voltage as the second control voltage to the second biasing controller,

wherein;

a magnitude of the difference between the product of the primary biasing fraction and the low system control voltage and the product of the secondary biasing fraction and the high system control voltage

is less than

a magnitude of the difference between the product of the primary biasing fraction and the high system control voltage and the product of the secondary biasing fraction and the low system control voltage

by only an amount sufficient for at least one of;

bringing spurious harmonic emissions of said second transistor switch when biased to the off state below a pre-identified upper limit of acceptable spurious harmonic emissions from the second transistor switch in the off state; and

bringing a linearity of the high power switch above a pre-identified lower limit of acceptable linearity for the high power switch.

16. A high power switch comprising:

a plurality of transistor switches comprising;

a first transistor switch; and

a second transistor switch,

biasing circuitry for providing, when the high power switch is in a first high power switch state;

on-state Vgsd at a on-state Vgsd level to the first transistor switch for biasing the first transistor switch in an on state; and

off-state Vgsd at a off-state Vgsd level to the second transistor switch for biasing the second transistor switch in an off state,

wherein a magnitude of the off-state Vgsd level is less than a magnitude of the on-state Vgsd level by only an amount sufficient for at least one of;

bringing spurious harmonic emissions of said second transistor switch when biased to the off state below a pre-identified upper limit of acceptable spurious harmonic emissions from the second transistor switch in the off state; and

bringing a linearity of the high power switch above a pre-identified lower limit of acceptable linearity for the high power switch.

17. A switch according to claim 16 wherein the on-state Vgsd level is a full-on on-state Vgsd level within reliability and operating constraints of each transistor switch of the plurality of transistor switches.

18. A switch according to claim 16 wherein said off-state Vgsd level is a fixed fraction of said on-state Vgsd level.

19. A switch according to claim 16 wherein each transistor switch of said plurality of switches is a silicon on insulator FET switch, and wherein said on-state Vgsd level is between 2.0 V and 2.5 V, and wherein the off-state Vgsd level is between 1.1 V and 1.5 V.

20. A switch according to claim 18 wherein when the high power switch is in the first high power switch state, the biasing circuitry provides on-state Vgsd to the first transistor switch by biasing at a gate of the first transistor switch with a on-state gate voltage at a fixed primary biasing fraction of a high system control voltage and biasing at a source-drain of the first transistor switch with a on-state source-drain voltage at a fixed secondary biasing fraction of a low system control voltage, and the biasing circuitry provides off-state Vgsd to the second transistor switch by biasing at a gate of the second transistor switch with a off-state gate voltage at the fixed primary biasing fraction of the low system control voltage and biasing at a source-drain of the second transistor switch with a off-state source-drain voltage at the fixed secondary biasing fraction of the high system control voltage.

21. A switch according to claim 20, wherein the biasing circuitry comprises at least one voltage divider circuit for providing the fixed primary biasing fraction and the fixed secondary biasing fraction of the high and low system control voltages.

22. A switch according to claim 16 further comprising:

an antenna,

a first input/output terminal; and

a second input/output terminal,

wherein the first transistor switch is located along a first signal path from the antenna to the first input/output terminal, and the second transistor switch is located along a second signal path from the antenna to the second input/output terminal, wherein when the high power switch is in the first high power switch state the biasing circuitry;

provides on-state Vgsd to the first transistor switch to provide a communication pathway between the antenna and the first input/output terminal; and

provides off-state Vgsd to the second transistor switch to isolate the antenna and the first input/output terminal from the second input/output terminal.

23. A switch according to claim 22 wherein the biasing circuitry is further for providing, when the high power switch is in a second high power switch state:

on-state Vgsd at the on-state Vgsd level to the second transistor switch for biasing the second transistor switch in an on state; and

off-state Vgsd at the off-state Vgsd level to the first transistor switch for biasing the first transistor switch in an off state,

wherein when the high power switch is in the second high power switch state, the biasing circuitry;

provides on-state Vgsd to the second transistor switch to provide a communication pathway between the antenna and the second input/output terminal; and

provides off-state Vgsd to the first transistor switch to isolate the antenna and the second input/output terminal from the first input/output terminal.

24. A switch according to claim 16 further comprising:

an antenna;

a first input/output terminal; and

a first ground connection,

wherein the first transistor switch is located along a signal path from the first input/output terminal to the antenna, and the second transistor switch is located along a shunt path from the first input/output terminal to the first ground connection, and wherein when the high power switch is in the first high power switch state, the biasing circuitry;

provides on-state Vgsd to the first transistor switch to provide a communication pathway between the first input/output terminal and the antenna; and

provides off-state Vgsd to the second transistor switch to isolate the antenna and the first input/output terminal from the first ground connection.

25. A switch according to claim 24 further comprising:

a second input/output terminal; and

a third transistor switch of the plurality of transistor switches,

wherein the third transistor switch is located along a signal path from the antenna to the second input/output terminal, wherein the biasing circuitry is further for providing, when the high power switch is in the first high power switch state, off-state Vgsd at the off-state Vgsd level to the third transistor switch for biasing the third transistor switch in the off state, and wherein when the high power switch is in the first high power switch state, the biasing circuit provides off-state Vgsd to the third transistor switch to isolate the antenna and the first input/output terminal from the second input/output terminal.

26. A switch according to claim 25 wherein the biasing circuitry is further for providing, when the high power switch is in a second high power switch state:

on-state Vgsd at the on-state Vgsd level to the second transistor switch for biasing the second transistor switch in an on state; and

off-state Vgsd at the off-state Vgsd level to the first transistor switch for biasing the first transistor switch in an off state, and

on-state Vgsd at the on-state Vgsd level to the third transistor switch for biasing the third transistor switch to an on state,

wherein when the high power switch is in the second high power switch state, the biasing circuitry;

provides on-state Vgsd to the second transistor switch to provide a shunt pathway between the first input/output terminal and the first ground connection;

provides on-state Vgsd to the third transistor switch to provide a communication pathway between the second input/output terminal and the antenna; and

provides off-state Vgsd to the first transistor switch to isolate the antenna and the second input/output switch from the first input/output terminal and the first ground connection.

27. A switch according to claim 25 further comprising:

a second ground connection; and

a fourth transistor switch of the plurality of transistor switches,

wherein the fourth transistor switch is located along a signal path from the second input/output terminal to the second ground connection, wherein the biasing circuit is further for providing, when the high power switch is in the first high power switch state, on-state Vgsd at the on-state Vgsd level to the fourth transistor switch for biasing the fourth transistor switch in the on state, wherein when the high power switch is in the first high power switch state, the biasing circuitry provides off-state Vgsd to the third transistor switch also to isolate the antenna and the first input/output terminal from the second ground connection, and the biasing circuitry provides an on-state Vgsd to the fourth transistor switch to provide a shunt pathway from the second input/output terminal to the second ground connection.

28. A switch according to claim 27 the biasing circuitry is further for providing, when the high power switch is in a second high power switch state:

on-state Vgsd at the on-state Vgsd level to the second transistor switch for biasing the second transistor switch in an on state;

off-state Vgsd at the off-state Vgsd level to the first transistor switch for biasing the first transistor switch in an off state;

on-state Vgsd at the on-state Vgsd level to the third transistor switch for biasing the third transistor switch to an on state; and

off-state Vgsd at the off-state Vgsd level to the fourth transistor switch for biasing the fourth transistor switch in an off state,

wherein when the high power switch is in a second high power switch state the biasing circuitry;

provides on-state Vgsd to the second transistor switch to provide a shunt pathway between the first input/output terminal and the first ground connection;

provides on-state Vgsd to the third transistor switch to provide a communication pathway between the second input/output terminal and the antenna;

provides off-state Vgsd to the first transistor switch to isolate the antenna and the second input/output terminal from the first input/output terminal and the first ground connection; and

provides off-state Vgsd to the fourth transistor switch to isolate the antenna and the second input/output switch from the second ground connection.

29. A high power switch comprising:

a first transistor switch;

a second transistor switch;

a first biasing controller for receiving a first control voltage and for;

biasing at a gate of the first transistor switch at a fixed primary biasing fraction of the first control voltage; and

biasing at a source-drain of the second transistor switch at a fixed secondary biasing fraction of the first control voltage,

a second biasing controller for receiving a second control voltage and for;

biasing at a source-drain of the first transistor switch at the fixed secondary biasing fraction of the second control voltage; and

biasing at a gate of the second transistor switch at the fixed primary biasing fraction of the second control voltage input,

wherein the first control voltage and the second control voltage are each a different one of a high system control voltage and a low system control voltage, and wherein;

a magnitude of the difference between the product of the primary biasing fraction and the low system control voltage and the product of the secondary biasing fraction and the high system control voltage

is less than

a magnitude of the difference between the product of the primary biasing fraction and the high system control voltage and the product of the secondary biasing fraction and the low system control voltage

by only an amount sufficient for at least one of;

bringing spurious harmonic emissions of said second transistor switch when biased to the off state below a pre-identified upper limit of acceptable spurious harmonic emissions from the second transistor switch in the off state; and

bringing a linearity of the high power switch above a pre-identified lower limit of acceptable linearity for the high power switch.