SHIFT REGISTER

• US 20110255653A1
• Filed: 12/27/2010
• Published: 10/20/2011
• Est. Priority Date: 04/19/2010
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Display Co., Ltd.
• Inventors: CHAE, Ji-Eun
• Granted Patent: US 9,601,073 B2
• Time in Patent Office: Days
• US Class Current: 377/79
• CPC Class Codes: G09G 2300/0408 Integration of the drivers onto the display substrate
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/0291 Details of output amplifiers or buffers arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence

Abstract

The present invention relates to a shift register in which a structure of a switching device of an output buffer unit is changed for reducing power consumption. The shift register includes a plurality of stages each having a plurality of switching devices, for forwarding a scan pulse in succession, wherein the at least one of the plurality of switching device has a first area at which a gate electrode thereof overlaps with a first electrode thereof with a size different from a second area at which the gate electrode overlaps with a second electrode thereof.

Claims

1. A shift register comprising:

a plurality of stages each having a plurality of switching devices, for forwarding a scan pulse in succession,

wherein at least one of the plurality of switching device has a first area at which a gate electrode thereof overlaps with a first electrode thereof being smaller than a second area at which the gate electrode overlaps with a second electrode thereof,

wherein a clock pulse is applied to the first electrode.

2. The shift register as claimed in claim 1, wherein the size of the first area is 10˜

15% smaller than the second area.

3. The shift register as claimed in claim 2, wherein the switching device includes;

a plurality of sub-first electrodes formed parallel to one another,

a connecting first electrode connecting the plurality of sub-first electrodes,

a plurality of sub-second electrodes formed parallel to one another, and

a connecting second electrode connecting the plurality of sub-second electrodes.

4. The shift register as claimed in claim 3, wherein the plurality of sub-first electrodes are formed to overlap with the gate electrode,

the connecting first electrode is formed not to overlap with the gate electrode, and

the plurality of sub-second electrodes and the connecting second electrode are formed to overlap with the gate electrode.

5. The shift register as claimed in claim 4, wherein each of the plurality of sub-first electrodes are formed between adjacent sub-second electrodes.

6. The shift register as claimed in claim 1, wherein each of the plurality of stages includes an output buffer unit for forwarding the scan pulse and an output control unit for controlling an output from the output buffer unit, and

the output buffer unit includes the switching device having the first area being smaller than the second area.

7. The shift register as claimed in claim 6, wherein the output buffer unit includes;

a pull-up switching device to be turned on/off depending on a signal state of a first node, and to connect one of clock transmission lines to an output terminal of the stage when the pull-up switching device is turned on,

a first pull-down switching device to be turned on/off depending on a signal state of a second node, and to connect the output terminal to a low potential voltage line when the first pull-down switching device is turned on, and

a second pull-down switching device to be turned on/off depending on a signal state of a third node, and to connect the output terminal to the low potential voltage line when the second pull-down switching device is turned on,

wherein the low potential voltage line transmits a low potential voltage and the clock transmission lines transmit a plurality of clock pulses having phases different from one another, and

the switching device having the first area being smaller than the second area is the pull-up switching device.

8. The shift register as claimed in claim 7, wherein the output control unit provided to an nth stage includes;

a first switching device to be turned on/off in response to a start pulse or a scan pulse from a (n−

1)th stage, and to connect the high potential voltage line to the first node when the first switching device is turned on,

a second switching device to be turned on/off in response to the scan pulse from a (n+1)th stage, and to connect the first node to the low potential voltage line when the second switching device is turned on,

a third switching device to be turned on/off depending on a signal state of the second node, and to connect the first node to the low potential voltage line when the third switching device is turned on,

a fourth switching device to be turned on/off according to a first AC voltage from a first AC power line, and to connect the first AC power line to the second node when the fourth switching device is turned on,

a fifth switching device to be turned on/off depending on a signal state of the first node, and to connect the second node to the low potential voltage line when the fifth switching device is turned on,

a sixth switching device to be turned on/off in response to the start pulse or the scan pulse from the (n−

1)th stage, and to connect the second node to the low potential voltage line when the sixth switching device is turned on,

a seventh switching device to be turned on/off depending on a signal state of the third node, and to connect the first node to the low potential voltage line when the seventh switching device is turned on,

an eighth switching device to be turned on/off according to a second AC voltage from a second AC power line, and to connect the second AC power line to the third node when the eighth switching device is turned on,

a ninth switching device to be turned on/off depending on a signal state of the first node, and to connect the third node to the low potential voltage line when the ninth switching device is turned on, and

a tenth switching device to be turned on/off in response to the start pulse or the scan pulse from the (n−

1)th stage, and to connect the third node to the low potential voltage line when the tenth switching device is turned on,

wherein the second AC voltage has a mode of a phase inverted by 180 degrees with respect to the first AC voltage,

the high potential voltage from the high potential voltage line is higher than the low potential voltage from the low potential voltage line, and

at least one of the first to tenth switching devices has the first area being smaller than the second area.