SELF-ALIGNED PROCESS FOR NANOTUBE/NANOWIRE FETs
First Claim
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1. A method of fabricating a semiconductor structure comprising:
- providing at least one gate region on a surface of a substrate, said at least one gate region comprising a layer of at least one one-dimensional nanostructure, a gate dielectric located on a surface of said at least one one-dimensional nanostructure and a gate electrode located on a surface of said gate dielectric, where said layer of at least one one-dimensional nanostructure is interposed between said substrate and said gate electrode;
forming at least one spacer on a surface of said layer of at least one one-dimensional nanostructure, wherein an inner edge of said at least one spacer is laterally abutting both a sidewall of said gate electrode and a sidewall of said gate dielectric; and
forming a metal carbide contact located on a surface of said substrate, wherein said metal carbide contact is aligned to and laterally abuts, but does not overlap, both a sidewall edge of said layer of at least one one-dimensional nanostructure and a sidewall edge of said at least one spacer.
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Abstract
A complementary metal oxide semiconductor (CMOS) device, e.g., a field effect transistor (FET), that includes at least one one-dimensional nanostructure that is typically a carbon-based nanomaterial, as the device channel, and a metal carbide contact that is self-aligned with the gate region of the device is described. The present invention also provides a method of fabricating such a CMOS device.
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Citations
20 Claims
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1. A method of fabricating a semiconductor structure comprising:
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providing at least one gate region on a surface of a substrate, said at least one gate region comprising a layer of at least one one-dimensional nanostructure, a gate dielectric located on a surface of said at least one one-dimensional nanostructure and a gate electrode located on a surface of said gate dielectric, where said layer of at least one one-dimensional nanostructure is interposed between said substrate and said gate electrode; forming at least one spacer on a surface of said layer of at least one one-dimensional nanostructure, wherein an inner edge of said at least one spacer is laterally abutting both a sidewall of said gate electrode and a sidewall of said gate dielectric; and forming a metal carbide contact located on a surface of said substrate, wherein said metal carbide contact is aligned to and laterally abuts, but does not overlap, both a sidewall edge of said layer of at least one one-dimensional nanostructure and a sidewall edge of said at least one spacer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method of fabricating a semiconductor structure comprising:
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providing at least one gate region on a surface of a substrate, said at least one gate region comprising a layer of at least one one-dimensional nanostructure, a gate dielectric located on a surface of said at least one one-dimensional nanostructure and a gate electrode located on a surface of said gate dielectric, where said layer of at least one one-dimensional nanostructure is interposed between said substrate and said gate electrode; forming at least one spacer on a surface of said layer of at least one one-dimensional nanostructure, wherein an inner edge of said at least one spacer is laterally abutting both a sidewall of said gate electrode and a sidewall of said gate dielectric; and forming a metal carbide contact on a surface of said substrate, wherein said metal carbide contact is aligned to and laterally abuts, but does not overlap, both a sidewall edge of said layer of at least one one-dimensional nanostructure and a sidewall edge of said at least one spacer, and wherein said at least one spacer does not overlap said metal carbide contact. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification