SELF-ALIGNED PROCESS FOR NANOTUBE/NANOWIRE FETs

• US 20110256675A1
• Filed: 06/03/2011
• Published: 10/20/2011
• Est. Priority Date: 01/07/2005
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Detavernier, Christophe G.M.M., Lavoie, Christian, Chen, Jia, Avouris, Phaedon, Wong, Hon-Sum Philip, Carruthers, Roy A.
• Granted Patent: US 8,119,466 B2
• Time in Patent Office: Days
• US Class Current: 438/197
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 29/0665 the shape of the body defining a nanostructure nanotechnology per se B82B
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H10K 10/464 Lateral top-gate IGFETs comprising only a single gate
• CPC Class Codes: H10K 85/221 Carbon nanotubes
• CPC Class Codes: Y10S 977/847 Surface modifications, e.g. functionalization, coating
• CPC Class Codes: Y10S 977/938 Field effect transistors, FETS, with nanowire- or nanotube-channel region

Abstract

A complementary metal oxide semiconductor (CMOS) device, e.g., a field effect transistor (FET), that includes at least one one-dimensional nanostructure that is typically a carbon-based nanomaterial, as the device channel, and a metal carbide contact that is self-aligned with the gate region of the device is described. The present invention also provides a method of fabricating such a CMOS device.

Claims

1. A method of fabricating a semiconductor structure comprising:

providing at least one gate region on a surface of a substrate, said at least one gate region comprising a layer of at least one one-dimensional nanostructure, a gate dielectric located on a surface of said at least one one-dimensional nanostructure and a gate electrode located on a surface of said gate dielectric, where said layer of at least one one-dimensional nanostructure is interposed between said substrate and said gate electrode;

forming at least one spacer on a surface of said layer of at least one one-dimensional nanostructure, wherein an inner edge of said at least one spacer is laterally abutting both a sidewall of said gate electrode and a sidewall of said gate dielectric; and

forming a metal carbide contact located on a surface of said substrate, wherein said metal carbide contact is aligned to and laterally abuts, but does not overlap, both a sidewall edge of said layer of at least one one-dimensional nanostructure and a sidewall edge of said at least one spacer.

2. The method of claim 1 wherein said layer of at least one one-dimensional nanostructure comprises at least one nanotube, at least one nanowire, or a combination of at least one nanotube and at least one nanowire.

3. The method of claim 1 wherein said layer of at least one one-dimensional nanostructure comprises a C-based nanomaterial.

4. The method of claim 1 wherein said layer of at least one one-dimensional nanostructure is formed by arc-discharge, laser ablation of a carbon target, or chemical vapor deposition.

5. The method of claim 1 wherein said substrate includes a semiconductor layer and a dielectric layer that has a least one region of a C-containing compound embedded therein located atop the semiconductor layer.

6. The method of claim 1 further comprising doping a portion of said layer of at least one one-dimensional nanostructure not protected by at least said gate electrode, said doping comprises electrostatic doping, ion implantation, or gas phase doping.

7. The method of claim 1 wherein said forming the metal carbide contact comprises forming a source/drain metal atop exposed portions of the layer of at least one one-dimensional nanostructure, and annealing.

8. The method of claim 7 further comprising forming a layer of metal compound atop the exposed portions of the layer of at least one one-dimensional nanostructure prior to forming the source/drain metal.

9. The method of claim 7 wherein said forming said source/drain metal comprises selecting at least one of Al, Si, Sc, Ti, V, Cr, Mn, Fe, Y, Zr, Nb, Mo, Hf, Ta and W and depositing the same.

10. The method of claim 9 wherein said depositing comprises an atomic layer deposition process or deposition from a carbon-containing target.

11. A method of fabricating a semiconductor structure comprising:

providing at least one gate region on a surface of a substrate, said at least one gate region comprising a layer of at least one one-dimensional nanostructure, a gate dielectric located on a surface of said at least one one-dimensional nanostructure and a gate electrode located on a surface of said gate dielectric, where said layer of at least one one-dimensional nanostructure is interposed between said substrate and said gate electrode;

forming at least one spacer on a surface of said layer of at least one one-dimensional nanostructure, wherein an inner edge of said at least one spacer is laterally abutting both a sidewall of said gate electrode and a sidewall of said gate dielectric; and

forming a metal carbide contact on a surface of said substrate, wherein said metal carbide contact is aligned to and laterally abuts, but does not overlap, both a sidewall edge of said layer of at least one one-dimensional nanostructure and a sidewall edge of said at least one spacer, and wherein said at least one spacer does not overlap said metal carbide contact.

12. The method of claim 11 wherein said layer of at least one one-dimensional nanostructure comprises at least one nanotube, at least one nanowire, or a combination of at least one nanotube and at least one nanowire.

13. The method of claim 11 wherein said layer of at least one one-dimensional nanostructure comprises a C-based nanomaterial.

14. The method of claim 11 wherein said layer of at least one one-dimensional nanostructure is formed by arc-discharge, laser ablation of a carbon target, or chemical vapor deposition.

15. The method of claim 11 wherein said substrate includes a semiconductor layer and a dielectric layer that has a least one region of a C-containing compound embedded therein located atop the semiconductor layer.

16. The method of claim 11 further comprising doping a portion of said layer of at least one one-dimensional nanostructure not protected by at least said gate electrode, said doping comprises electrostatic doping, ion implantation, or gas phase doping.

17. The method of claim 11 wherein said forming the metal carbide contact comprises forming a source/drain metal atop exposed portions of the layer of at least one one-dimensional nanostructure, and annealing.

18. The method of claim 17 further comprising forming a layer of metal compound atop the exposed portions of the layer of at least one one-dimensional nanostructure prior to forming the source/drain metal.

19. The method of claim 17 wherein said forming said source/drain metal comprises selecting at least one of Al, Si, Sc, Ti, V, Cr, Mn, Fe, Y, Zr, Nb, Mo, Hf, Ta and W and depositing the same.

20. The method of claim 17 wherein said depositing comprises an atomic layer deposition process or deposition from a carbon-containing target.