Multiple Deposition, Multiple Treatment Dielectric Layer For A Semiconductor Device

• US 20110256682A1
• Filed: 04/15/2010
• Published: 10/20/2011
• Est. Priority Date: 04/15/2010
• Status: Abandoned Application

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Ling, Wu, Yu, Hongyu, Tao, Hun-Jan, Chiu, Yuan-Hung, Hsu, Kuang-Yuan, Lee, Da-Yuan, Lee, Wei-Yang, Yu, Xiong-Fei
• Application Number:
  US12/761,159
• Publication Number:
  US 20110256682A1
• Time in Patent Office: Days
• US Class Current: 438/287
• CPC Class Codes: H01L 21/02181 the material containing hafnium, e.g. HfO2
• CPC Class Codes: H01L 21/0228 deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
• CPC Class Codes: H01L 21/02337 treatment by exposure to a gas or vapour
• CPC Class Codes: H01L 21/02348 treatment by exposure to UV light
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Abstract

A method is provided for fabricating a semiconductor device. A semiconductor substrate is provided. A first high-k dielectric layer is formed on the semiconductor substrate. A first treatment is performed on the high-k dielectric layer. In an embodiment, the treatment includes a UV radiation in the presence of O₂ and/or O₃. A second high-k dielectric layer is formed on the treated first high-k dielectric layer. A second treatment is performed on the second high-k dielectric layer. In an embodiment, the high-k dielectric layer forms a gate dielectric layer of a field effect transistor.

Claims

1. A method of fabricating a semiconductor device, comprising:

providing a semiconductor substrate;

forming a first high-k dielectric layer on the semiconductor substrate;

performing a first treatment on the first high-k dielectric layer, thereby forming a first treated high-k dielectric layer;

forming a second high-k dielectric layer on the first treated high-k dielectric layer; and

performing a second treatment on the second high-k dielectric layer.

2. The method of claim 1, wherein the first treatment is at least one of a UV radiation in an O₂ environment and a UV radiation in an O₃ environment.

3. The method of claim 2, wherein the second treatment is at least one of a UV radiation in an O₂ environment and a UV radiation in an O₃ environment.

4. The method of claim 2, wherein the first treatment is greater than approximately 30 seconds.

5. The method of claim 1, wherein the first and second high-k dielectric layer have the same composition.

6. The method of claim 1, further comprising:

forming a metal gate overlying the second high-k dielectric layer.

7. The method of claim 1, further comprising:

forming a dummy gate structure on the semiconductor substrate.

8. The method of claim 1, wherein at least one of the first treatment and the second treatment includes a thermal anneal.

9. The method of claim 1, further comprising:

forming an interfacial layer on the substrate underlying the first high-k dielectric layer.

10. The method of claim 1, wherein the first treatment includes treating the surface of the first high-k dielectric layer with dilute ozone.

11. A method, comprising:

forming a first portion of a gate dielectric layer on a semiconductor substrate;

performing a first treatment on the first portion of the gate dielectric layer;

forming a second portion of the gate dielectric layer directly on the treated first portion;

performing a second treatment on the second portion of the gate dielectric layer, and

forming a gate electrode on the gate dielectric layer.

12. The method of claim 11, wherein the forming the first portion of the gate dielectric layer includes performing at least two cycles of an atomic layer deposition (ALD) process.

13. The method of claim 11, wherein the forming the second portion of the gate dielectric layer includes performing at least two cycles of an atomic layer deposition (ALD) process.

14. The method of claim 11, further comprising:

depositing a third portion of the gate dielectric layer on the treated second portion; and

performing a third treatment on the third portion of the gate dielectric layer.

15. The method of claim 11, wherein the gate dielectric layer is selected from the group consisting of hafnium oxide (HfO₂), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), and combinations thereof.

16. A method of semiconductor fabrication, comprising:

forming a dummy gate structure on a semiconductor substrate;

forming a source and drain region adjacent the dummy gate structure;

thereafter, removing the dummy gate structure to form a trench;

depositing a first portion of a high-k dielectric layer on the semiconductor substrate including in the trench;

treating the first portion of the high-k dielectric layer;

depositing a second portion of the high-k dielectric layer on the substrate overlying the treated first portion of the high-k dielectric layer;

treating the second portion of the high-k dielectric layer; and

forming a metal gate on the treated second portion of the high-k dielectric layer.

17. The method of claim 16, wherein the treating the first portion includes a first treatment and the treating the second portion includes a second treatment, and wherein the first and second treatments are selected from the group consisting of a chemical treatment, a thermal anneal treatment, and a radiation treatment.

18. The method of claim 16, wherein the depositing the first portion of the high-k dielectric layer deposits less than ten atomic layers of the high-dielectric layer.

19. The method of claim 16, further comprising:

forming an interfacial layer on the semiconductor substrate in the trench prior to forming the first portion of the high-k dielectric layer.

20. The method of claim 16, wherein the high-k dielectric layer is hafnium oxide (HfO₂).