APPARATUS, SYSTEM, AND METHOD FOR DESTAGING CACHED DATA

• US 20110258391A1
• Filed: 04/15/2011
• Published: 10/20/2011
• Est. Priority Date: 12/06/2007
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Fusion-IO Incorporated (Western Digital Corporation)
• Inventors: Flynn, David, Atkisson, David
• Granted Patent: US 9,104,599 B2
• Time in Patent Office: Days
• US Class Current: 711/118
• CPC Class Codes: G06F 11/108 Parity data distribution in semiconductor storages, e.g. in SSD
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0866 for peripheral storage systems, e.g. disk cache
• CPC Class Codes: G06F 12/0875 with dedicated cache, e.g. instruction or stack
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 2211/103 Hybrid, i.e. RAID systems with parity comprising a mix of RAID types
• CPC Class Codes: G06F 2212/1024 Latency reduction
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 2212/222 Non-volatile memory
• CPC Class Codes: G06F 2212/604 Details relating to cache allocation
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: H04L 12/403 with centralised control, e.g. polling
• CPC Class Codes: H04L 12/4625 Single bridge functionality, e.g. connection of two networks over a single bridge
• CPC Class Codes: H04L 67/1097 for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS]
• CPC Class Codes: H05K 7/1444 Complex or three-dimensional-arrangements; Stepped or dual mother boards

Abstract

An apparatus, system, and method are disclosed for destaging cached data. A controller detects one or more write requests to store data in a backing store. The cache controller sends the write requests to a storage controller for a nonvolatile solid-state storage device. The storage controller receives the write requests and caches the data associated with the write requests in the nonvolatile solid-state storage device by appending the data to a log of the nonvolatile solid-state storage device. The log includes a sequential, log-based structure preserved in the nonvolatile solid-state storage device. The cache controller receives at least a portion of the data from the storage controller in a cache log order and destages the data to the backing store in the cache log order. The cache log order comprises an order in which the data was appended to the log of the nonvolatile solid-state storage device.

Claims

1. A method for destaging cached data, the method comprising:

caching write data in a nonvolatile solid-state cache by appending the data to a log of the nonvolatile solid-state cache, the log comprising a sequential, log-based structure preserved in the nonvolatile solid-state cache; and

destaging at least a portion of the data from the nonvolatile solid-state cache to the backing store in a cache log order, the cache log order comprising an order in which the data was appended to the log of the nonvolatile solid-state cache.

2. The method of claim 1, further comprising destaging at least a portion of the data from the nonvolatile solid-state cache to the backing store in a sequential backing store address order.

3. The method of claim 2, further comprising determining a destaging pressure for the nonvolatile solid-state cache, the destaging pressure comprising a level of demand for destaging cached data of the nonvolatile solid-state cache.

4. The method of claim 3, further comprising adjusting a destaging rate to satisfy the destaging pressure by adjusting a ratio of data to destage in the cache log order to data to destage in the sequential backing store address order.

5. The method of claim 2, wherein the sequential backing store address order comprises one or more ranges of address contiguous data, the contiguous data in a range sequentially ordered by backing store address.

6. The method of claim 2, wherein destaging data in sequential backing store address order comprises traversing a mapping structure that maps backing store addresses to locations on physical storage media of the nonvolatile solid-state cache and selecting a destage data range such that members of the data range have contiguous and sequential backing store addresses.

7. The method of claim 2, wherein each backing store address directly maps to a logical address of the nonvolatile solid-state cache, and wherein logical addresses of the cache are independent of physical storage media addresses of the nonvolatile solid-state cache, and wherein a logical address space of the nonvolatile solid-state cache exceeds a storage capacity of the physical storage media of the nonvolatile solid-state cache.

8. The method of claim 2, wherein the nonvolatile solid-state cache comprises a lower destage rate destaging in the cache log order than destaging in the sequential backing store address order and the backing store comprises a higher write rate destaging in the sequential backing store address order than destaging in the cache log order.

9. The method of claim 2, further comprising preventing destaging of data within a predefined distance of an append point of the log of the nonvolatile solid-state cache.

10. The method of claim 2, wherein determining the destaging pressure comprises determining a difference between an actual amount of dirty write data of the nonvolatile solid-state cache and a target amount of dirty write data of the nonvolatile solid-state cache, dirty write data comprising write data cached in the nonvolatile solid-state cache that has not been destaged to the backing store.

11. The method of claim 1, wherein destaging in cache log order comprises destaging data region by region, the regions ordered in cache log order.

12. The method of claim 11, further comprising re-ordering data of a region to a backing store address order such that the regions destage in the cache log order and data within a region destages to the backing store in the backing store address order for addresses within a region.

13. The method of claim 1, wherein the log of the nonvolatile solid-state cache comprises multiple append points for writing cached data, the multiple append points comprising at least one append point for writing dirty data and at least one append point for writing clean data, dirty data comprising write data that has not been destaged to the backing store and clean data comprising data that is stored in the backing store.

14. An apparatus to destage cached data, the apparatus comprising:

a cache controller in communication with a backing store, the cache controller configured to detect one or more write requests to store data in the backing store;

the cache controller further configured to send the write requests to a storage controller for a nonvolatile solid-state storage device, the storage controller receiving the write requests and caching the data associated with the write requests in the nonvolatile solid-state storage device by appending the data to a log of the nonvolatile solid-state storage device, the log comprising a sequential, log-based structure preserved in the nonvolatile solid-state storage device; and

the cache controller further configured to receive at least a portion of the data from the storage controller in a cache log order and to destage the data to the backing store in the cache log order, the cache log order comprising an order in which the data was appended to the log of the nonvolatile solid-state storage device.

15. The apparatus of claim 14, wherein the cache controller is further configured to receive at least a portion of the data from the storage controller in a sequential backing store address order and to destage the data to the backing store in the sequential backing store address order.

16. The apparatus of claim 15, wherein the cache controller is further configured to determine a destaging pressure for the nonvolatile solid-state cache, the destaging pressure comprising a level of demand for destaging cached data of the nonvolatile solid-state cache, the cache controller requesting the data from the storage controller in the sequential backing store address order in response to the destaging pressure satisfying a predefined destaging pressure criteria.

17. The apparatus of claim 14, further comprising a backing store controller for the backing store, the cache controller interfacing with the backing store controller to destage the data to the backing store, wherein the cache controller, the storage controller, and the backing store controller each comprise a device driver executing on a host computer system.

18. A system to destage cached data, the system comprising:

a processor;

a nonvolatile solid-state storage device preserving a log, the log comprising a sequential, log-based structure;

a backing store;

one or more communications buses, the nonvolatile solid-state storage device and the backing store in communication with the processor over the one or more communication buses;

a cache controller in communication with the backing store, the cache controller configured to detect one or more write requests to store data in the backing store;

the cache controller further configured to send the write requests to a storage controller for the nonvolatile solid-state storage device, the storage controller receiving the write requests and caching the data associated with the write requests in the nonvolatile solid-state storage device by appending the data to the log of the nonvolatile solid-state storage device; and

the cache controller further configured to receive at least a portion of the data from the storage controller in a cache log order and to destage the data to the backing store in the cache log order, the cache log order comprising an order in which the data was appended to the log of the nonvolatile solid-state storage device.

19. The system of claim 18, wherein the cache controller is further configured to receive at least a portion of the data from the storage controller in a sequential backing store address order and to destage the data to the backing store in the sequential backing store address order.

20. The system of claim 18, further comprising a host computer system, the host computer system comprising the processor, wherein the cache controller and the storage controller each comprise a device driver executing on the processor of the host computer system.