METHOD, SYSTEM AND INTEGRATED CIRCUIT FOR ENABLING ACCESS TO A MEMORY ELEMENT

• US 20110258462A1
• Filed: 01/05/2009
• Published: 10/20/2011
• Est. Priority Date: 01/05/2009
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Beattie, Derek, Scobie, James Andrew Collier, Robertson, Alistair
• Granted Patent: US 8,966,286 B2
• Time in Patent Office: Days
• US Class Current: 713/193
• CPC Class Codes: G06F 21/31 User authentication
• CPC Class Codes: G06F 21/79 in semiconductor storage media, e.g. directly-addressable memories

Abstract

A system comprises signal processing logic that is operably coupled to at least one memory element and is arranged to enable access to the at least one memory element. The signal processing logic is arranged to receive a security key, generate a system key using the received security key and a system specific seed, perform a comparison of the generated system key to a reference key stored in an area of memory of the at least one memory element. The signal processing logic is also arranged to configure a level of access to the at least one memory element based at least partly on the comparison of the generated system key to the reference key stored in memory.

Claims

1. A system comprising:

signal processing logic, the signal processing logic being operably coupled to at least one memory element and arranged to enable access to the at least one memory element;

wherein the signal processing logic is arranged to receive a security key, generate a system key using the received security key and a system specific seed, perform a comparison of the generated system key to a reference key stored in an area of memory of the at least one memory element, and configure a level of access to the at least one memory element based at least partly on the comparison of the generated system key to the reference key stored in memory.

2. The system of claim 1 wherein the signal processing logic is arranged to cause access to the at least one memory element to be at least partially restricted if the comparison of the generated system key to the reference key stored in memory results in a mismatch there between.

3. The system of claim 1 wherein the signal processing logic is arranged to enable unrestricted access to the at least one memory element if the comparison of the generated system key to the reference key stored in memory results in a match there between.

4. The system of claim 1 wherein the system further comprises a hardware encryption engine arranged to receive the security key and the system specific seed, and to generate the system key there from.

5. The system of claim 4 wherein the hardware encryption engine forms a part of signal processing logic.

6. The system of claim 1 wherein the system key is generated using one of:

an Advanced Encryption Standard (AES) encryption algorithm, a TINY encryption algorithm.

7. The system of claim 1 wherein the system specific seed comprises a non-memory mapped device identifier.

8. The system of claim 7 wherein the system specific seed comprises x-y wafer coordinates and a wafer lot number for use by the signal processing logic.

9. The system of claim 1 wherein the signal processing logic comprises censorship logic arranged to configure the level of access to the at least one memory element by setting a censorship control word in the area of memory.

10. The system of claim 1 wherein the signal processing logic is arranged to implement a time delay between receiving security keys.

11. The system of claim 1 wherein the at least one memory element comprises non-volatile memory.

12. The system of claim 1 wherein the signal processing logic is arranged to receive the security key via at least one of a test port and a network interface.

13. The system of claim 12 wherein the signal processing logic is arranged to receive the security key via at least one of:

a Joint Test Action Group (JTAG) port;

a Controller Area Network (CAN) interface; and

a Serial Communication Interface (SCI).

14. The system of claim 1 wherein the system comprises part of an automotive system

15. (canceled)

16. A method for enabling access to at least one memory element within a signal processing system, the method comprising:

receiving a security key;

generating a system key using the received security key and a system specific seed;

performing a comparison of the generated system key to a reference key stored in an area of memory of the at least one memory element; and

configuring a level of access to the at least one memory element based at least partly on the comparison of the generated system key to the reference key stored in memory.

19. The method of claim 16 wherein the system key is generated using one of:

an Advanced Encryption Standard (AES) encryption algorithm, a TINY encryption algorithm.

20. The method of claim 16 wherein the system specific seed comprises x-y wafer coordinates and a wafer lot number for use by the signal processing logic.

21. The method of claim 16 wherein the system specific seed comprises a non-memory mapped device identifier.

17. A computer-readable storage element comprising executable program code for programming signal processing logic, the computer-readable storage element comprising program code for:

receiving a security key;

generating a system key using the received security key and a system specific seed;

performing a comparison of the generated system key to a reference key stored in an area of memory of at least one memory element operably coupled to the signal processing logic; and

configuring a level of access to the at least one memory element based at least partly on the comparison of the generated system key to the reference key stored in memory.

18. The computer-readable storage element of claim 17, wherein the computer-readable storage element comprises at least one of a hard disk, a CD-ROM, an optical storage device, a magnetic storage device, a Read Only Memory, ROM, a Programmable Read Only Memory, PROM, an Erasable Programmable Read Only Memory, EPROM, an Electrically Erasable Programmable Read Only Memory, EEPROM, and a Flash memory.