Multi-Level Signal Memory with LDPC and Interleaving

• US 20110258509A1
• Filed: 06/27/2011
• Published: 10/20/2011
• Est. Priority Date: 03/31/2006
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Aditya Ramamoorthy
• Inventors: Ramamoorthy, Aditya
• Granted Patent: US 8,869,014 B2
• Time in Patent Office: Days
• US Class Current: 714/752
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: H03M 13/11 using multiple parity bits
• CPC Class Codes: H03M 13/255 with Low Density Parity Check [LDPC] codes

Abstract

Embodiments of the present invention provide multi-level signal memory with LDPC and interleaving. Thus, various embodiments of the present invention provide a memory apparatus that includes a memory block comprising a plurality of memory cells, each memory cell adapted to operate with multi-level signals. Such a memory apparatus also includes a low density parity check (LDPC) coder to LDPC code data values to be written into the memory cells and an interleaver adapted to apply bit interleaved code modulation (BICM) to the LDPC coded data values to generate BICM coded data values. Other embodiments may be described and claimed,

Claims

1. A memory apparatus comprising:

a memory block comprising a plurality of memory cells, each memory cell configured to operate with multi-level signals;

a low density parity check (LDPC) coder configured to LDPC encode data values to provide LDPC encoded data values to be written into the memory cells;

an interleaver configured to interleave the LDPC encoded data values with bit interleaved code modulation to generate interleaved LDPC encoded data values;

a pulse amplitude modulator operatively coupled to the interleaver and the memory block, the pulse amplitude modulator configured to modulate the interleaved LDPC encoded data values for the memory block; and

a mapper configured to map the interleaved LDPC encoded data values to modulation codes in accordance with a constellation map.

2. The memory apparatus of claim 1, further comprising a controller configured to control (i) encoding by the LDPC coder, (ii) interleaving by the interleaver, and (iii) receiving of the multi-level signals by the memory block.

3. The memory apparatus of claim 1, wherein the constellation map is based upon Gray code.

4. The memory apparatus of claim 3, wherein the constellation map comprises 8 modulation codes

5. The memory apparatus of claim 1, further comprising a channel block that comprises (i) the interleaver and (ii) the pulse amplitude modulator.

6. The memory apparatus of claim 1, further comprising a channel block that comprises (i) the interleaver and (ii) at least one of the LDPC coder or the mapper.

7. The memory apparatus of claim 1, wherein at least the memory block is configured as a flash memory device.

8. The memory apparatus of claim 1, wherein the memory block comprises one of a floating gate device, oxide-nitride-oxide (ONO) charge trapping device or a phase change memory device.

9. The memory apparatus of claim 1, further comprising a digital bus interface operatively coupled to each of the pulse amplitude modulator and the memory block, wherein the pulse amplitude modulator is configured to serially output multi-level signals to the memory block.

10. The memory apparatus of claim 1, further comprising a de-interleaver operatively coupled to the memory block, the de-interleaver configured to de-interleave interleaved LDPC encoded data values from multi-level signals received from the memory block to provide de-interleaved LDPC encoded data values.

11. The memory apparatus of claim 10, further comprising an LDPC decoder operatively coupled to the de-interleaver, the LDPC decoder configured to decode data values from the de-interleaved LDPC encoded data values.

12. The memory apparatus of claim 11, further comprising a channel block that comprises (i) the de-interleaver and (ii) the LDPC decoder.

13. A method comprising:

encoding a plurality of multi-level signal data values with corresponding low density parity (LDPC) codes to provide LDPC encoded multi-level signal data values;

interleaving the LDPC encoded multi-level signal data values with bit interleaved code modulation to provide interleaved LDPC encoded multi-level signal data values;

outputting, using multi-level signals, the interleaved LDPC encoded multi-level signal data values for storage in a memory block;

modulating the interleaved LDPC encoded data values for the memory block; and

mapping the interleaved LDPC encoded multi-level signal data values to modulation codes in accordance with a constellation map.

14. The method of claim 13, wherein the constellation map is based upon Gray code.

15. The method of claim 14, wherein the constellation map comprises 8 constellation points.

16. The method of claim 13, wherein the modulating is performed with a pulse amplitude modulator (PAM).

17. A method comprising:

receiving, from a memory block comprising a plurality of memory cells, an encoded multi-level signal data value, wherein the encoded multi-level signal data value has been encoded with a low density parity check code (LDPC) and interleaved with bit interleaved code modulation;

de-interleaving the encoded multi-level signal data value to provide a de-interleaved encoded multi-level signal data value; and

decoding the de-interleaved encoded multi-level signal data value to recover a multi-level signal data value,

wherein the encoded multi-level signal data value has also been mapped to a modulation code in accordance with a constellation map.

18. The method of claim 17, wherein:

a set of least significant bits have been mapped to a modulation code corresponding to a lowest transmission voltage level; and

a set of most significant bits have been mapped to a modulation code corresponding to a highest transmission voltage level.

19. The method of claim 17, wherein the constellation map is based upon Gray code.

20. The method of claim 19, wherein the constellation map comprises 8 constellation points.