Semiconductor Devices Including a Transistor With Elastic Channel

• US 20110260136A1
• Filed: 04/19/2011
• Published: 10/27/2011
• Est. Priority Date: 04/27/2010
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Ji-myoung, Kim, Dong-won, Kim, Min-sang
• Granted Patent: US 8,525,147 B2
• Time in Patent Office: Days
• US Class Current: 257/9
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 29/1606 Graphene
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/78684 having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys H01L29/7869 takes precedence
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A semiconductor device that may control a formation of a channel is disclosed. The semiconductor device includes a gate region including a first area, an insulating layer disposed on portions of a top surface of the gate region corresponding to both ends portions of the first area, first and second electrodes formed on the insulating layer to be spaced apart from each other, an elastic conductive layer disposed between the first and second electrodes and the insulating layer and having a shape that varies according to an electrostatic force based on voltages applied to the first electrode, the second electrode, and the gate region, and a gate insulating region disposed between the elastic conductive layer and the first area of the gate region.

Claims

1. A semiconductor device comprising an elastic channel transistor, the semiconductor device comprising:

a gate region comprising a first area;

an insulating layer disposed on portions of a top surface of the gate region corresponding to both side end portions of the first area;

first and second electrodes formed on the insulating layer to be spaced apart from each other;

an elastic conductive layer disposed between the first and second electrodes and the insulating layer and having a shape that varies according to an electrostatic force based on voltages applied to the first electrode, the second electrode, and the gate region; and

a gate insulating region disposed between the elastic conductive layer and the first area of the gate region.

2. The semiconductor device of claim 1, wherein the elastic conductive layer comprises graphene.

3. The semiconductor device of claim 1, wherein the gate insulating region is a cavity defined by the gate region and the elastic conductive layer.

4. The semiconductor device of claim 1, wherein the gate insulating region is formed of a silicon oxide film, a metal oxide film, a metal silicon oxide film, or a combination thereof.

5. The semiconductor device of claim 1, wherein the first area is formed to have a round cross-sectional shape that is inwardly curved.

6. The semiconductor device of claim 1, wherein the elastic conductive layer is charged by a first control voltage applied to the first electrode,

wherein when a voltage applied to the second electrode has substantially the same polarity as a voltage of the first control voltage that does not change a polarity of the elastic conductive layer charged by the first control voltage, a channel is determined to be formed in the elastic conductive layer based on the first control voltage and a second control voltage applied to the gate region.

7. The semiconductor device of claim 6, wherein when the second control voltage has a polarity opposite to a polarity of the first control voltage, the elastic conductive layer is spaced apart from the gate region not to form the channel.

8. The semiconductor device of claim 6, wherein when the second control voltage has substantially the same polarity as a polarity of the first control voltage, the elastic conductive layer has a channel formed therein adjacent to the gate region.

9. The semiconductor device of claim 1, further comprising a support structure formed on the first and second electrodes and that defines a cavity over the elastic conductive layer.

10. The semiconductor device of claim 1, wherein when a power supply voltage is not applied to the elastic conductive layer, the elastic conductive layer maintains its shape right before the power supply voltage is applied to the elastic conductive layer due to its elasticity.

11. The semiconductor device of claim 1, wherein the elastic conductive layer is formed by an exfoliation process that involves attaching single-crystal graphite to a top surface of the insulating layer and attaching part of the single-crystal graphite to the insulating layer.

12. A semiconductor device comprising an elastic channel transistor, the semiconductor device comprising:

a gate region that includes a top surface and a recessed area having a round cross-sectional shape that is inwardly curved and that is configured to receive a gate voltage;

an insulating layer that is disposed on the top surface of the gate region, the insulating layer being disposed on portions of the top surface that are adjacent the recessed area;

a first electrode that is formed on the insulating layer and that is configured to receive a control voltage;

a second electrode that is formed on the insulating layer and that is spaced apart from the first electrode by the recessed area that is therebetween;

an elastic conductive layer comprising graphene that is disposed between the first and second electrodes and the insulating layer and that includes a shape that varies according to an electrostatic force generated between the elastic conductive layer and the gate region based on the control voltage and the gate voltage; and

a gate insulating region that is disposed between the elastic conductive layer and the recessed area of the gate region

13. The semiconductor device of claim 12, wherein the elastic channel transistor is formed on the first and second electrodes and a cavity over the elastic conductive layer, the device further comprising a support structure over the cavity that is supported by a porous film.

14. The semiconductor device of claim 12, wherein

when the control voltage has the same polarity as a polarity of the gate voltage, or when a sum of the control voltage and the gate voltage is greater than a predetermined pull-out voltage, the elastic conductive layer is spaced apart from the gate electrode so as not to form a conductive channel, and

when the control voltage has a polarity opposite to the polarity of the gate voltage, or when a difference between the control voltage and the gate voltage is greater than a predetermined pull-in voltage, the elastic conductive layer is attached to the gate region to form a conductive channel.

15. The semiconductor device of claim 14, wherein the pull-in voltage and the pull-out voltage are determined based on a physical friction force between the elastic conductive layer and the gate insulating region, and an electrical conductivity and elasticity of the elastic conductive layer.

16. The semiconductor device of claim 12, wherein the shape of the elastic conductive layer is substantially the same shape as a shape of the first area of the gate region.

17. The semiconductor device of claim 12, further comprising:

a word line that extends in a first direction and that is electrically connected to the gate region; and

a bit line that extends in a second direction that is different from the first direction and that is electrically connected to the first electrode.

18. The semiconductor device of claim 17, wherein when a word line voltage is applied to the word line and a bit line voltage having substantially the same polarity as a polarity of the word line voltage is applied to the bit line, the elastic conductive layer has a conductive channel formed therein adjacent the gate region, and

wherein the bit line voltage is provided to the second electrode in response to an output of a logic element.

19. The semiconductor device of claim 17, wherein when a word line voltage is applied to the word line and a bit line voltage having a polarity substantially opposite to a polarity of the word line voltage is applied to the bit line, the elastic conductive layer is spaced apart from the gate region and does not to form a conductive channel, and

wherein the bit line voltage is not provided to the second electrode.

20. The semiconductor device of claim 17, further comprising:

a first p-n junction region connected between the word line and the gate region;

a second p-n junction region including a first terminal connected to the gate region; and

a logic element connected to a second terminal of the second p-n junction region.