PHASE INTERLEAVING CONTROL METHOD FOR A MULTI-CHANNEL REGULATOR SYSTEM

• US 20110260765A1
• Filed: 04/15/2011
• Published: 10/27/2011
• Est. Priority Date: 04/21/2010
• Status: Active Grant

• Current Assignee: Richtek Technology Corporation (MediaTek, Inc.)
• Original Assignee: Richtek Technology Corporation (MediaTek, Inc.)
• Inventors: CHEN, ISAAC Y., LU, SHAO-HUNG, CHEN, AN-TUNG
• Granted Patent: US 8,451,887 B2
• Time in Patent Office: Days
• US Class Current: 327/202
• CPC Class Codes: H02M 3/1586 switched with a phase shift, i.e. interleaved
• CPC Class Codes: H03K 19/00346 Modifications for eliminating interference or parasitic voltages or currents
• CPC Class Codes: H03K 7/08 Duration or width modulation ; Duty cycle modulation

Abstract

A multi-channel regulator system includes serially connected PWM integrated circuits, each of which determines a PWM signal for a respective channel to operate therewith, and individually controls its operation mode according to whether or not an external clock is detected. Therefore, each channel will not be limited to operate under a constant mode and could become a master channel or a slave channel. Additionally, each of the PWM integrated circuits generates a phase shifted synchronous clock for its next channel during it is enabled, and thus all the channels operate in a synchronous but phase interleaving manner.

Claims

1. A phase interleaving control method for a multi-channel regulator system including a plurality of pulse width modulation integrated circuits connected in series, each said pulse width modulation integrated circuit determining a pulse width modulation signal for a respective channel, the method comprising operating each said pulse width modulation integrated circuit to perform the steps of:

(A) during a first state detecting if any external clock appears at an input pin of said pulse width modulation integrated circuit;

(B) if a first clock is detected in the step A, then performing the steps of;

transiting to a second state for a slave mode;

triggering the pulse width modulation signal with the first clock; and

generating a second clock synchronous to but phase interleaved with the first clock, and outputting the second clock through an output pin of said pulse width modulation integrated circuit; and

(C) if no external clock is detected in the step A, then performing the steps of;

transiting to a third state for a master mode;

triggering the pulse width modulation signal with an internal clock of said pulse width modulation integrated circuit; and

generating a third clock synchronous to but phase interleaved with the internal clock, and outputting the third clock through said output pin.

2. The method of claim 1, further comprising the step of defining a phase delay based on a phase setting device inside or outside said pulse width modulation integrated circuit.

3. The method of claim 2, wherein the second clock is generated using the phase delay.

4. The method of claim 2, wherein the third clock is generated using the phase delay.

5. The method of claim 1, further comprising the step of defining a phase delay based on a phase setting device on said output pin.

6. The method of claim 5, wherein the second clock is generated using the phase delay.

7. The method of claim 5, wherein the third clock is generated using the phase delay.

8. The method of claim 5, further comprising the step of making said output pin at a preset state during a fourth state.

9. The method of claim 1, further comprising the step of defining a phase delay based on a resistor on said output pin.

10. The method of claim 9, wherein the second clock is generated using the phase delay.

11. The method of claim 9, wherein the third clock is generated using the phase delay.

12. The method of claim 9, further comprising the step of making said output pin at a preset state during a fourth state.

13. The method of claim 1, further comprising the steps of:

if a fourth clock appears at said input pin during the master mode, controlling a phase of the pulse width modulation signal; and

when a phase difference between the pulse width modulation signal and the fourth clock becomes less than a threshold, transiting to the second state.

14. The method of claim 1, further comprising the step of transiting to the third state if the first clock disappears for a threshold time during the slave mode.

15. A phase interleaving control method for a multi-channel regulator system including a plurality of pulse width modulation integrated circuits connected in series, each said pulse width modulation integrated circuit determining a pulse width modulation signal for a respective channel, the method comprising operating each said pulse width modulation integrated circuit to perform the steps of:

(A) detecting a phase setting device to define a phase delay during a power on reset of said pulse width modulation integrated circuit;

(B) after the power on reset, if a first clock coming from a previous channel is detected, transiting to a first state for a slave mode and triggering the pulse width modulation signal with the first clock, otherwise transiting to a second state for a master mode and triggering the pulse width modulation signal with an internal clock of said pulse width modulation integrated circuit;

(C) during the slave mode, generating a second clock synchronous to but phase interleaved with the first clock using the phase delay, and once a cycle variation of the first clock reaches a threshold, transiting to the second state and triggering the pulse width modulation signal with the internal clock; and

(D) during the master mode, generating a third clock synchronous to but phase interleaved with the internal clock using the phase delay, and once a fourth clock coming from the previous channel is detected, transiting to the first state and triggering the pulse width modulation signal with the fourth clock.

16. The method of claim 15, wherein the step D comprises the steps of:

upon detecting the fourth clock, controlling a phase of the pulse width modulation signal; and

when a phase difference between the pulse width modulation signal and the fourth clock becomes less than a threshold, transiting to the first state.

17. The method of claim 15, further comprising the step of transiting to a third state if a sleep signal is detected after the power on reset.

18. The method of claim 17, further comprising the step of transiting to the second state if the sleep signal disappears for a preset time during the third state.

19. The method of claim 15, further comprising the step of transiting to a third state if a sleep signal is detected during the first state.

20. The method of claim 19, further comprising the step of transiting to the second state if the sleep signal disappears for a preset time during the third state.

21. The method of claim 15, further comprising the step of transiting to a third state if a sleep signal is detected during the second state.

22. The method of claim 21, further comprising the step of transiting to the second state if the sleep signal disappears for a preset time during the third state.